CHIRON’s effort in hybrid CMOS-spin-wave computing fits into a wider research effort in the semiconductor device community to find new ways to extend Moore’s law beyond the physical scaling limitations of CMOS transistors. Some of the approaches target the replacement of (complex) logic gates rather than individual transistors. This follows current design automation methods that use logic gates as building blocks for circuit design. If these logic gates are formed by individual transistors but rely on different principles, for example using different physical entities to encode information such as magnetic degrees of freedom used in spintronics, the logic gates may follow different scaling laws and can potentially be made much smaller than implementations based on transistors. Hence, the long-term goal of CHIRON’s consortium members is to realize spin-wave circuits that are (much) smaller than their CMOS counterparts.
CHIRON has thus set four concrete objectives. The target specifications of objectives 1–3 followed a roadmap with two technology nodes (TN) during the project.
The first objective concerns the magnetoelectric transducers, both for spin-wave generation as well as detection. Both the proof-of-principle of a scalable transducer with an FBAR design as well as the specifications clearly go beyond the state-of-the-art at the start of the project.
The second objective addresses the scalability of the spin-wave majority gates and the inverters. Miniaturized spin-wave circuits (majority gates, inverters) require the usage of spin waves with short wavelengths. High group velocities improve the computing throughput. Low attenuation lengths are of interest for large circuits although circuit area scaling will alleviate the issue.
The third objective combined objectives 1 and 2 to achieve miniaturized majority gates and inverters. This constitutes a proof of concept of a scalable/scaled spin-wave computing technology. The targeted output voltage would be in a range close to being detected by conventional CMOS periphery.
The fourth and final objective intends to fill the gaps in the circuit design methodology with the goal to develop a methodology to design “arbitrary” logic circuits in spin-wave technology. Such concrete circuits can then be used to benchmark the hybrid SW-CMOS technology in terms of area and throughput. When magnetoelectric transducers are included in the benchmarking methodology, also the computing energy can be estimated.
The above discussions show how CHIRON’s objectives aim at extending the state of the art in multiple aspects from device demonstrators to circuit design concepts. An achievement of all objectives would in principle allow CHIRON to fabricate a spin-wave circuit with electrical input and output transducers. Such a circuit was not yet the goal of CHIRON but will be addressed in a follow-up project, as discussed below. Nonetheless, all elemental building blocks for the circuit would have been demonstrated together with a clear methodology how to combine them in circuits. In the following, we will discuss in detail how close we have come to this final project goal, which objectives have been achieved and which issues remain after the end of CHIRON.
