Periodic Reporting for period 1 - CHIRON (Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics)
Berichtszeitraum: 2018-05-01 bis 2019-04-30
CHIRON envisions spin wave computing to complement and eventually replace CMOS in future microelectronic circuits. Spin wave computing has the potential for significant power and area reduction per computing throughput while reducing cost by alleviating lithography requirements. Currently, however, no complete concept for a full “spin wave computer” exists that includes logic, memory, interconnects, clock, etc, with implementations based only on magnetic signals. Hence, as a first step, CHIRON envisions hybrid spin wave–CMOS circuits that are integrated alongside CMOS. More precisely, CHIRON aims to demonstrate logic circuits based on spin waves that can be embedded in a CMOS periphery that provides (long-distance) interconnects, data memory, clock circuitry, etc.
To achieve its goals, CHIRON has set four concrete objectives. To facilitate the achievement of the objectives and mitigate risk, the target specifications of transducers and devices follow a roadmap with two technology nodes (TN) during the project. The first TN (TN1) has more relaxed specifications, followed by a second TN (TN2) that satisfies the final target specifications.
OBJ1 Develop ME and MF nanoresonators as SW transducers based on an FBAR design.
Target specications:
TN1: lateral dimension of 500 nm; resonance frequency 6 GHz; quality factor 5.
TN2: lateral dimension of 100 nm; resonance frequency 15 GHz; quality factor 20.
OBJ2 Develop waveguides for the propagation of SWs with sub-µm wavelengths.
Target specications:
TN1: wavelength 500 nm; group velocity 103 m/s; attenuation length 1 µm.
TN2: wavelength 100 nm; group velocity 103 m/s; attenuation length 1 µm.
OBJ3 Demonstrate an inverter as well as a three-input majority gate using the above
transducers as well as an optimised waveguide. Demonstrate frequency multiplexing.
Target specications:
TN1: characteristic lateral dimension 500 nm; output voltage 10 mV;
computation time 10 ns.
TN2: characteristic lateral dimension 100 nm; output voltage 50 mV;
computation time 1 ns.
OBJ4 Design hybrid SW–CMOS circuits and benchmark them against standard CMOS using calibrated compact models of transducers and logic gates as well as interconnects.
To achieve its goals, CHIRON has set four concrete objectives. To facilitate the achievement of the objectives and mitigate risk, the target specifications of transducers and devices follow a roadmap with two technology nodes (TN) during the project. The first TN (TN1) has more relaxed specifications, followed by a second TN (TN2) that satisfies the final target specifications.
OBJ1 Develop ME and MF nanoresonators as SW transducers based on an FBAR design.
Target specications:
TN1: lateral dimension of 500 nm; resonance frequency 6 GHz; quality factor 5.
TN2: lateral dimension of 100 nm; resonance frequency 15 GHz; quality factor 20.
OBJ2 Develop waveguides for the propagation of SWs with sub-µm wavelengths.
Target specications:
TN1: wavelength 500 nm; group velocity 103 m/s; attenuation length 1 µm.
TN2: wavelength 100 nm; group velocity 103 m/s; attenuation length 1 µm.
OBJ3 Demonstrate an inverter as well as a three-input majority gate using the above
transducers as well as an optimised waveguide. Demonstrate frequency multiplexing.
Target specications:
TN1: characteristic lateral dimension 500 nm; output voltage 10 mV;
computation time 10 ns.
TN2: characteristic lateral dimension 100 nm; output voltage 50 mV;
computation time 1 ns.
OBJ4 Design hybrid SW–CMOS circuits and benchmark them against standard CMOS using calibrated compact models of transducers and logic gates as well as interconnects.
In the first 12 months of the project, CHIRON consortium members have designed, fabricated, and characterized magnetoelectric nanoresonators, based on nanoscale bulk acoustic resonators. In addition, two terminal inverter devices have also been fabrication and are currently characterized. Complementary work on multiferroic devices is ongoing. In a next step, majority gates will be manufactured, their operation will be demonstrated, and their performance will be assessed.
CHIRON has demonstrated two different transducer devices with the potential for further scaling to the final device specifications at the end of the project.
To achieve its goals, CHIRON has set four concrete objectives. To facilitate the achievement of the objectives and mitigate risk, the target specifications of transducers and devices follow a roadmap with two technology nodes (TN) during the project. The first TN (TN1) has more relaxed specifications, followed by a second TN (TN2) that satisfies the final target specifications. In the first 12 months of the project, the work has focused on OBJ1 and 2 with TN1.
OBJ5 Develop ME and MF nanoresonators as SW transducers based on an FBAR design.
Target specications:
TN1: lateral dimension of 500 nm; resonance frequency 6 GHz; quality factor
OBJ6 Develop waveguides for the propagation of SWs with sub-µm wavelengths.
Target specications:
TN1: wavelength 500 nm; group velocity 103 m/s; attenuation length 1 µm
CHIRON has demonstrated two different transducer devices with the potential for further scaling to the final device specifications at the end of the project.
To achieve its goals, CHIRON has set four concrete objectives. To facilitate the achievement of the objectives and mitigate risk, the target specifications of transducers and devices follow a roadmap with two technology nodes (TN) during the project. The first TN (TN1) has more relaxed specifications, followed by a second TN (TN2) that satisfies the final target specifications. In the first 12 months of the project, the work has focused on OBJ1 and 2 with TN1.
OBJ5 Develop ME and MF nanoresonators as SW transducers based on an FBAR design.
Target specications:
TN1: lateral dimension of 500 nm; resonance frequency 6 GHz; quality factor
OBJ6 Develop waveguides for the propagation of SWs with sub-µm wavelengths.
Target specications:
TN1: wavelength 500 nm; group velocity 103 m/s; attenuation length 1 µm
Most current research on future nanoelectronic devices focuses on the complementary metal-oxide-semiconductor (CMOS) transistors that are at the heart of present-day technology. However, there are also more paradigm-shifting approaches that rather aim at replacing entire logic gates or complex circuits. The vision of CHIRON is to complement and, in the long term, replace CMOS by spin wave (SW) computing circuits. SW computing is a part of the emerging eld of magnonics3 and has both high potential for further miniaturised microelectronic circuits and lower cost per function—enabling the continuation of Moore’s law—as well as the reduction of power consumption. Hence, we envision SW computing as an ultimately-scaled low-power microelectronic technology. The main objective of CHIRON is to demonstrate both the feasibility and viability of hybrid SW–CMOS circuits. Such hybrid circuits are highly promising to complement CMOS-based microelectronics in future technology nodes. Our long-term vision beyond the hybrid circuits in CHIRON is to build a full SW computer. This requires both SW logic as well as memory. The development of SW memory and its interface with SW logic circuits shall be the content of a follow-up project.
In SW computing, the information is coded in the phase of SWs (magnons) and information processing is based on interference. This allows especially for the efcient realisation of majority gates.The SW computing circuit allows for a higher area efciency even though the smallest (critical) dimension in the circuit is larger than that of the CMOS circuit. Hence, an area gain can be realised even with more relaxed lithography and thus at lower cost. Initial benchmarking of hybrid SW–CMOS circuits including a full CMOS periphery assuming a critical dimension of 100 nm indicates that complex circuits can be realised with an improved area efciency (per computing throughput) of about 5× over CMOS circuits (10 nm technology node). Moreover, the hybrid SW–CMOS circuit uses about two orders of magnitude less energy per throughput. Thus, SW computing appears very promising as a beyond-CMOS technology and its realisation will provide an important breakthrough to even further miniaturise microelectronic circuits as well as for ultralow-power electronics that have the potential to revolutionise portable or autonomous high-performance computing devices. Currently, no proof of principle of such a hybrid technology has been demonstrated due to scientic and technological obstacles that need to be overcome.
In SW computing, the information is coded in the phase of SWs (magnons) and information processing is based on interference. This allows especially for the efcient realisation of majority gates.The SW computing circuit allows for a higher area efciency even though the smallest (critical) dimension in the circuit is larger than that of the CMOS circuit. Hence, an area gain can be realised even with more relaxed lithography and thus at lower cost. Initial benchmarking of hybrid SW–CMOS circuits including a full CMOS periphery assuming a critical dimension of 100 nm indicates that complex circuits can be realised with an improved area efciency (per computing throughput) of about 5× over CMOS circuits (10 nm technology node). Moreover, the hybrid SW–CMOS circuit uses about two orders of magnitude less energy per throughput. Thus, SW computing appears very promising as a beyond-CMOS technology and its realisation will provide an important breakthrough to even further miniaturise microelectronic circuits as well as for ultralow-power electronics that have the potential to revolutionise portable or autonomous high-performance computing devices. Currently, no proof of principle of such a hybrid technology has been demonstrated due to scientic and technological obstacles that need to be overcome.