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Technology and hardware for neuromorphic computing

Project description

New ways to integrate emerging memories to enable neuromorphic computing systems

Artificial intelligence (AI) and machine learning are used today for computing all kinds of data, making predictions and solving problems. These are processes based increasingly on deep neuronal network (DNN) models. As the volume of produced data slow down machines and consume greater amounts of energy, there is a new generation of neural units. The spiking neural networks (SNNs) incorporate biologically-feasible spiking neurons with their temporal dynamics. The EU-funded TEMPO project will leverage emerging memory technology to design new innovative technological solutions that make data integration simpler and easier via new neuronal DNN and SNN computing engines. Reduced core computational operational systems’ neuromorphic algorithms will serve as demonstrators.

Objective

Massive adoption of computing in all aspects of human activity has led to unprecedented growth in the amount of data generated. Machine learning has been employed to classify and infer patterns from this abundance of raw data, at various levels of abstraction. Among the algorithms used, brain-inspired, or “neuromorphic”, computation provides a wide range of classification and/or prediction tools. Additionally, certain implementations come about with a significant promise of energy efficiency: highly optimized Deep Neural Network (DNN) engines, ranging up to the efficiency promise of exploratory Spiking Neural Networks (SNN). Given the slowdown of silicon-only scaling, it is important to extend the roadmap of neuromorphic implementations by leveraging fitting technology innovations. Along these lines, the current project aims to sweep technology options, covering emerging memories and 3D integration, and attempt to pair them with contemporary (DNN) and exploratory (SNN) neuromorphic computing paradigms. The process- and design-compatibility of each technology option will be assessed with respect to established integration practices. Core computational kernels of such DNN/SNN algorithms (e.g. dot-product/integrate-and-fire engines) will be reduced to practice in representative demonstrators.

Call for proposal

H2020-ECSEL-2018-2-RIA-two-stage

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Sub call

H2020-ECSEL-2018-2-RIA-two-stage-1

Coordinator

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Net EU contribution
€ 1 907 062,50
Address
Kapeldreef 75
3001 Leuven
Belgium

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Region
Vlaams Gewest Prov. Vlaams-Brabant Arr. Leuven
Activity type
Research Organisations
Links
Other funding
€ 3 541 687,50

Participants (19)