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Technology and hardware for neuromorphic computing

Periodic Reporting for period 2 - TEMPO (Technology and hardware for neuromorphic computing)

Reporting period: 2020-05-01 to 2021-04-30

The fundamental goal of the TEMPO project is to broaden the applicability of integrated neuromorphic hardware by improving energy efficiency with emerging memory technologies in novel neuromorphic hardware implementations.
• The main objective of TEMPO is to build a European eco-system around the development, production and application of neuromorphic hardware through an efficient cross-fertilization between major European foundries, chip design, system houses, application companies and research partners, as presented by the European Leader Group (ELG) to the European Commissioner Maria Gabriel on 19 June 2018 in the report “Boosting Electronics Value Chains in Europe”.
• TEMPO is a first step in the direction of creating an implementation plan that supports the creation of a pan-European research infrastructure for advanced computing technologies. A major goal of the project is to bring together the world class expertise and infrastructures of Imec, LETI and Fraunhofer-Verbunds Mikroelektronik, and together with semiconductor companies and system houses to explore the possibilities of the developed technology. In the project, seven use-cases will be assessed in key domains where Europe is strong (automotive, space and health). The aim is to re-inforce and keep strong leadership in these areas by already bringing industry in contact with future technologies at low TRL level.
In year 1, the work in the project focused along 2 dimensions mainly:
• Design of test vehicles and process flows in the RTOs to enable the process technology pathfinding work later in the project to optimally leverage embedded Non-Volatile Memories for Neuromorphic and AI applications
• Design of core building blocks and accelerator architectures targeted to leverage the memory technologies in application demonstrators.
In the second year the work on the hardware has continued and application and algorithm design is well underway:
• Manufacturing basewafers at foundries for further processing at the RTOs in WP2 and WP3, as well as continued design and tape outs of accelerator chips in WP4. At the same time, in WP5 the RTOs have aligned on procedures for contamination checks, MES data exchange, to allow smooth collaborative processing of these types of wafers in the future, paving the way to the future Hardware TEF (Test and Experiment Facilities) for AI at EU level.
• In parallel, the application and demonstration work has kicked off in full speed: for all use cases requirements have been defined, algorithms have been explored and baseline reference implementations have been built.
In year 3, the consortium will work to combine both these hardware and application results to enable demonstration of energy efficient accelerators for the different use cases defined in the project.
The main goal is to show and quantify by the demonstrators built that the technology the project builds upon enables substantial benefits in compute power, energy efficiency to run advanced neuromorphic and neural net based applications in resource constrained hardware (in terms of energy, latency or area)
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