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Architecting More Than Moore – Wireless Plasticity for Heterogeneous Massive Computer Architectures


Die-level system simulator considering wired and wireless interconnect

A beta of the die-level simulator will be released to the partners and to the community. Contains a short tutorial.

Setup of public project website communication channels

In this first deliverable, we will setup the website (tentatively: and public repository where papers and software will be uploaded. Moreover, we will setup the main communication channels in social media.

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A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL

Author(s): Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs, 2020, Page(s) 1-1, ISSN 1549-7747
DOI: 10.1109/tcsii.2020.3005246

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Author(s): Xavier Timoneda, Sergi Abadal, Antonio Franques, Dionysios Manessis, Jin Zhou, Josep Torrellas, Eduard Alarcon, Albert Cabellos-Aparicio
Published in: IEEE Transactions on Communications, Issue 68/5, 2020, Page(s) 3247-3258, ISSN 0090-6778
DOI: 10.1109/tcomm.2020.2973988

Wave Propagation and Channel Modeling in Chip-Scale Wireless Communications: A Survey From Millimeter-Wave to Terahertz and Optics

Author(s): Sergi Abadal, Chong Han, Josep Miquel Jornet
Published in: IEEE Access, Issue 8, 2020, Page(s) 278-293, ISSN 2169-3536
DOI: 10.1109/access.2019.2961849

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations

Author(s): Alexandre Levisse, Marc Bocquet, Marco Rios, Mouhamad Alayan, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, David Atienza, Jean-Michel Portal
Published in: IEEE Access, Issue 8, 2020, Page(s) 109297-109308, ISSN 2169-3536
DOI: 10.1109/access.2020.3000867

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors

Author(s): Loris Duch, Miguel Peon-Quiros, Pieter Weckx, Alexandre Levisse, Ruben Braojos, Francky Catthoor, David Atienza
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Issue 28/10, 2020, Page(s) 2122-2133, ISSN 1063-8210
DOI: 10.1109/TVLSI.2020.3003471

BLADE: An in-Cache Computing Architecture for Edge Devices

Author(s): William Andrew Simon, Yasir Mahmood Qureshi, Marco Rios, Alexandre Levisse, Marina Zapater, David Atienza
Published in: IEEE Transactions on Computers, Issue 69/9, 2020, Page(s) 1349-1363, ISSN 0018-9340
DOI: 10.1109/tc.2020.2972528

Understanding the Impact of On-chip Communication on DNN Accelerator Performance

Author(s): Robert Guirado, Hyoukjun Kwon, Eduard Alarcon, Sergi Abadal, Tushar Krishna
Published in: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, Page(s) 85-88
DOI: 10.1109/icecs46596.2019.8964858

Enabling mixed-precision quantized neural networks in extreme-edge devices

Author(s): Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
Published in: Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020, Page(s) 217-220
DOI: 10.1145/3387902.3394038

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

Author(s): Halima Najibi, Jorge Hunter, Alexandre Levisse, Marina Zapater, Miroslav Vasic, David Atienza
Published in: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, Page(s) 18-23
DOI: 10.1109/isvlsi49217.2020.00014

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Author(s): Halima Najibi, Alexandre Levisse, Marina Zapater, Mohamed M. Sabry Aly, David Atienza
Published in: Proceedings of the 2020 on Great Lakes Symposium on VLSI, 2020, Page(s) 513-518
DOI: 10.1145/3386263.3406923

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

Author(s): Alexandre Levisse, Marco Rios, Miguel Peon-Quiros, David Atienza
Published in: ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2020, Page(s) 1549-1552
DOI: 10.1109/icassp40776.2020.9054524

A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference

Author(s): Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
Published in: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, Page(s) 512-517
DOI: 10.1109/isvlsi49217.2020.000-5