Architecting More Than Moore – Wireless Plasticity for Heterogeneous Massive Computer Architectures | WiPLASH | Project | Results | H2020 | CORDIS

Risultati finali

High performance graphene on wafer scale including encapsulation

Experimental demonstration of high-mobility graphene encapsulated (for instance, sandwiched between hexagonal boron nitride layers) and integrated at the wafer scale.

Full transceiver/antenna subsystem with high performance ready for measurements

Experimental demonstration of the fabrication process for the integration of antenna and transceiver subsystems.

First co-integration of graphene antennas with full custom SiGe transceivers

Experimental demonstration of the co-integration of the antenna and SiGe transceivers within the same system.

Wireless communication performance and cost models

Report with area and power models from T32 as well as link latency and throughput models from T33

Graphene integration design report

Report with designs for the graphene component integration in WP2 and a quantitative analysis of the performance advantages with respect to conventional technologies

Channel model

Channel characterization models for inpackage wireless propagation in the frequency and time domains including coveragemultipath analysis

Heterogeneous System-on-Chip

This report will deliver the full systemonchip RTL and netlists as well as an evaluation of its performance and energy efficiency

Adaptive protocol stack

Report delivering a comprehensive analysis of designs considered at the PHYMACNET layers with broad assessments of performancecost of the wireless network within package

Tunable and switchable graphene multiantenna report

Simulations of the achievable performance of tunability and beamsteering capabilities of graphenebased multiantenna solutions

AI applications workloads

This report will deliver the specification of AI applications requirements necessary to derive initial architecture specifications

Die-level exploration at design-time/runtime

Exploration optimization strategies task mapping strategies DVFS onthefly reconfiguration Identification of efficiencyperformancethermal tradeoffs

Package-level exploration

Exploration of machinelearning based strategies to optimize the task mapping allocation exploration of dielevel optimization strategies at package level and identified tradeoffs

Die-level system simulator considering wired and wireless interconnect

A beta of the die-level simulator will be released to the partners and to the community. Contains a short tutorial.

Release of the open-source simulator with benchmark architectures

It contains architectures optimized for a set of applications and can be updated until M36 (or beyond) with users’ feedback.

SiGe BiCMOS test devices

Tx/Rx devices at three spot frequencies in the 60-312 GHz range will be provided to experimentally assess intra-/inter-chip communication channels.

In-Memory accelerator

This report will deliver the in-memory accelerator specifications, as well as models for integration of the accelerators into the PULP clusters and high-level simulation models.

Setup of public project website communication channels

In this first deliverable, we will setup the website (tentatively: www.wiplash.eu) and public repository where papers and software will be uploaded. Moreover, we will setup the main communication channels in social media.

Pubblicazioni

A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics

Autori: Fabio Montagna, Stefan Mach, Simone Benatti, Angelo Garofalo, Gianmarco Ottavi, Luca Benini, Davide Rossi, Giuseppe Tagliavini
Pubblicato in: IEEE Transactions on Parallel and Distributed Systems, Numero 10459219, 2022, Pagina/e 1038-1053, ISSN 1045-9219
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2021.3101764

Metasurface‐Programmable Wireless Network‐On‐Chip

Autori: Mohammadreza F. Imani; Sergi Abadal; Philipp del Hougne
Pubblicato in: Advanced Science, Numero 21983844, 2022, ISSN 2198-3844
Editore: Wiley
DOI: 10.1002/advs.202201458

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

Autori: David Atienza Alonso; Alexandre Levisse; Marco Antonio Rios; Giovanni Ansaloni; Flavio Ponzina
Pubblicato in: IEEE Transactions on Emerging Topics in Computing, Numero 2, 2023, Pagina/e 358 - 372, ISSN 2168-6750
Editore: IEEE Computer Society
DOI: 10.1109/tetc.2023.3237914

Gem5-X : A Many-Core Heterogeneous Simulation Platform for Architectural Exploration and Optimization

Autori: Qureshi, Yasir Mahmood, William Andrew Simon, Marina Zapater, Katzalin Olcoz, and David Atienza
Pubblicato in: Transactions on Architecture and Code Optimization (TACO), Numero 15443566, 2021, Pagina/e 1-27, ISSN 1544-3566
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3461662

WHYPE: A Scale-Out Architecture With Wireless Over-the-Air Majority for Scalable In-Memory Hyperdimensional Computing

Autori: Robert Guirado; Abbas Rahimi; Geethan Karunaratne; Eduard Alarcón; Abu Sebastian; Sergi Abadal
Pubblicato in: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Numero 3, 2023, ISSN 2156-3365
Editore: IEEE
DOI: 10.1109/jetcas.2023.3243064

Graphene‐Based Microwave Circuits: A Review

Autori: Mohamed Saeed; Paula Palacios; Muh‐Dey Wei; Eyyub Baskent; Chun‐Yu Fan; Burkay Uzlu; Kun‐Ta Wang; Andreas Hemmetter; Zhenxing Wang; Daniel Neumaier; Max C. Lemme; Renato Negra
Pubblicato in: Advanced Materials, Numero 15214095, 2022, Pagina/e 2108473, ISSN 1521-4095
Editore: Wiley
DOI: 10.18154/rwth-2022-03131

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

Autori: Davide Rossi, Francesco Conti, Manuel Eggiman, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
Pubblicato in: IEEE Journal of Solid-State Circuits, Numero 00189200, 2022, Pagina/e 127-139, ISSN 0018-9200
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/jssc.2021.3114881

Graphene in 2D/3D Heterostructure Diodes for High Performance Electronics and Optoelectronics

Autori: Zhenxing Wang; Andreas Hemmetter; Burkay Uzlu; Mohamed Saeed; Ahmed Hamed; Satender Kataria; Renato Negra; Daniel Neumaier; Max C. Lemme
Pubblicato in: Advanced Electronic Materials, Numero 2199160X, 2021, Pagina/e 2001210, ISSN 2199-160X
Editore: Wiley
DOI: 10.1002/aelm.202001210

A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL

Autori: Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini
Pubblicato in: IEEE Transactions on Circuits and Systems II: Express Briefs, 2020, Pagina/e 1-1, ISSN 1549-7747
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsii.2020.3005246

Roadmap on energy harvesting materials

Autori: Vincenzo Pecunia, S Ravi P Silva2, Jamie D Phillips, Elisa Artegiani, Alessandro Romeo, Hongjae Shim,, Jongsung Park, Jin Hyeok Kim, Jae Sung Yun, Gregory C Welch, Bryon W Larson, Myles Creran, Audrey Laventure, Kezia Sasitharan, Natalie Flores-Diaz, Marina Freitag, Jie Xu, Thomas M Brown, Benxuan Li1, Yiwen Wang, Zhe Li1, Bo Hou1,Behrang H Hamadani, Emmanuel Defay, Veronika Kovacova, Sebastjan Gl
Pubblicato in: Journal of Physics: Materials, Numero 6, 2023, ISSN 2515-7639
Editore: IOP
DOI: 10.1088/2515-7639/acc550

E2CNN: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices

Autori: Ponzina, Flavio, Miguel Peón-Quirós, Andreas Burg, and David Atienza
Pubblicato in: Transactions on Computers, Numero 00189340, 2021, Pagina/e 1199-1212, ISSN 0018-9340
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2021.3061086

Darkside: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training

Autori: Angelo Garofalo; Yvan Tortorella; Matteo Perotti; Luca Valente; Alessandro Nadalini; Luca Benini; Davide Rossi; Francesco Conti
Pubblicato in: IEEE Open Journal of the Solid-State Circuits Society, Numero 26441349, 2022, ISSN 2644-1349
Editore: IEEE
DOI: 10.1109/ojsscs.2022.3210082

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Autori: Xavier Timoneda, Sergi Abadal, Antonio Franques, Dionysios Manessis, Jin Zhou, Josep Torrellas, Eduard Alarcon, Albert Cabellos-Aparicio
Pubblicato in: IEEE Transactions on Communications, Numero 68/5, 2020, Pagina/e 3247-3258, ISSN 0090-6778
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcomm.2020.2973988

Wave Propagation and Channel Modeling in Chip-Scale Wireless Communications: A Survey From Millimeter-Wave to Terahertz and Optics

Autori: Sergi Abadal, Chong Han, Josep Miquel Jornet
Pubblicato in: IEEE Access, Numero 8, 2020, Pagina/e 278-293, ISSN 2169-3536
Editore: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2019.2961849

Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion

Autori: Amlan Ganguly, Sergi Abadal, Ishan Thakkar, Natalie Enright Jerger, Marc Riedel, Masoud Babaie, Rajeev Balasubramonian, Abu Sebastian, Sudeep Pasricha, Baris Taskin
Pubblicato in: IEEE Micro, Numero 02721732, 2022, Pagina/e 40-49, ISSN 0272-1732
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/mm.2022.3150684

Design Considerations for a Low-Power Fully Integrated MMIC Parametric Upconverter in SiGe BiCMOS

Autori: Paula Palacios, Mohamed Saeed, Renato Negra
Pubblicato in: IEEE Journal of Solid-State Circuits, Numero 6, 2023, Pagina/e 1519 - 1534, ISSN 1558-173X
Editore: IEEE
DOI: 10.1109/jssc.2023.3238550

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations

Autori: Alexandre Levisse, Marc Bocquet, Marco Rios, Mouhamad Alayan, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, David Atienza, Jean-Michel Portal
Pubblicato in: IEEE Access, Numero 8, 2020, Pagina/e 109297-109308, ISSN 2169-3536
Editore: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2020.3000867

Using Algorithmic Transformations and Sensitivity Analysis to Unleash Approximations in CNNs at the Edge

Autori: Flavio Ponzina, Giovanni Ansaloni, Miguel Peón-Quirós, David Atienza
Pubblicato in: Micromachines, Numero 2072666X, 2022, ISSN 2072-666X
Editore: Multidisciplinary Digital Publishing Institute (MDPI)
DOI: 10.3390/mi13071143

Survey on Terahertz Nanocommunication and Networking: A Top-Down Perspective

Autori: Filip Lemic; Sergi Abadal; Wouter Tavernier; Pieter Stroobant; Didier Colle; Eduard Alarcon; Johann M. Marquez-Barja; Jeroen Famaey
Pubblicato in: IEEE Journal on Selected Areas in Communications, Numero 07338716, 2021, Pagina/e 1506-1543, ISSN 0733-8716
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.48550/arxiv.1909.05703

Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors

Autori: Sergi Abadal; Robert Guirado; Hamidreza Taghvaee; Akshay Jain; Elana Pereira de Santana; Peter Haring Bolivar; Mohamed Saeed; Renato Negra; Zhenxing Wang; Kun-Ta Wang; Max C. Lemme; Joshua Klein; Marina Zapater; Alexandre Levisse; David Atienza; Davide Rossi; Francesco Conti; Martino Dazzi; Geethan Karunaratne; Irem Boybat; Abu Sebastian
Pubblicato in: IEEE Wireless Communications, Numero 15361284, 2022, ISSN 1536-1284
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.48550/arxiv.2011.04107

2D materials for future heterogeneous electronics

Autori: Max C. Lemme; Deji Akinwande; Cedric Huyghebaert; Christoph Stampfer
Pubblicato in: Nature Communications, Numero 20411723, 2022, Pagina/e 1392, ISSN 2041-1723
Editore: Nature Publishing Group
DOI: 10.5281/zenodo.6834164

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

Autori: Joshua Klein; Irem Boybat; Yasir Qureshi; Martino Dazzi; Alexandre Levisse; Giovanni Ansaloni; Marina Zapater; Abu Sebastian; David Atienza
Pubblicato in: IEEE Transactions on Computers, Numero 7, 2022, Pagina/e 1985 - 1998, ISSN 1557-9956
Editore: IEEE
DOI: 10.1109/tc.2022.3230285

Overflow-free compute memories for edge AI acceleration

Autori: Ponzina, Flavio ; Rios, Marco Antonio ; Levisse, Alexandre Sébastien Julien ; Ansaloni, Giovanni ; Atienza Alonso, David
Pubblicato in: ACM Transactions on Embedded Computing Systems, Numero 5, 2023, Pagina/e 1-23, ISSN 1539-9087
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3609387

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

Autori: Hayate Okuhara; Ahmed Elnaqib; Martino Dazzi; Pierpaolo Palestri; Simone Benatti; Luca Benini; Davide Rossi
Pubblicato in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Numero 10638210, 2021, Pagina/e 1800-1811, ISSN 1063-8210
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tvlsi.2021.3108806

Zero-Bias Power-Detector Circuits based on MoS2 Field-Effect Transistors on Wafer-Scale Flexible Substrates

Autori: Eros Reato, Paula Palacios, Burkay Uzlu, Mohamed Saeed, Annika Grundmann, Zhenyu Wang, Daniel S. Schneider, Zhenxing Wang, Michael Heuken, Holger Kalisch, Andrei Vescan, Alexandra Radenovic, Andras Kis, Daniel Neumaier, Renato Negra, Max C. Lemme
Pubblicato in: Advanced Materials, Numero 15214095, 2022, Pagina/e 2108469, ISSN 1521-4095
Editore: Wiley
DOI: 10.1002/adma.202108469

Multi-Channel Near-Field Terahertz Communications Using Reprogrammable Graphene-Based Digital Metasurface

Autori: Kasra Rouhi; Seyed Ehsan Hosseininejad; Sergi Abadal; Mohsen Khalily; Rahim Tafazolli
Pubblicato in: IEEE/OSA Journal of Lightwave Technology, Numero 07338724, 2021, Pagina/e 6893-6907, ISSN 0733-8724
Editore: Optical Society of America
DOI: 10.1109/jlt.2021.3105911

Computing Graph Neural Networks: A Survey from Algorithms to Accelerators

Autori: Sergi Abadal; Akshay Jain; Robert Guirado; Jorge López-Alonso; Eduard Alarcón
Pubblicato in: ACM Computing Surveys, Numero 03600300, 2022, Pagina/e 191:1-38, ISSN 0360-0300
Editore: Association for Computing Machinary, Inc.
DOI: 10.48550/arxiv.2010.00130

DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs

Autori: Alessio Burrello; Angelo Garofalo; Nazareno Bruschi; Giuseppe Tagliavini; Davide Rossi; Francesco Conti
Pubblicato in: IEEE Transactions on Computers, Numero 00189340, 2021, Pagina/e 1253 - 1268, ISSN 0018-9340
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.48550/arxiv.2008.07127

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing

Autori: Conti, Francesco; Paulin, Gianna; Rossi, Davide; Di Mauro, Alfio; Rutishauser, Georg; Ottavi, Gianmarco; Eggimann, Manuel; Okuhara, Hayate; Benini, Luca
Pubblicato in: IEEE Journal of Solid-State Circuits, Numero 6, 2023, Pagina/e 1-15, ISSN 0000-0000
Editore: IEEE
DOI: 10.48550/arxiv.2305.08415

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors

Autori: Loris Duch, Miguel Peon-Quiros, Pieter Weckx, Alexandre Levisse, Ruben Braojos, Francky Catthoor, David Atienza
Pubblicato in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Numero 28/10, 2020, Pagina/e 2122-2133, ISSN 1063-8210
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TVLSI.2020.3003471

Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters

Autori: Florian Glaser, Giuseppe Tagliavini, Davide Rossi, Germain Haugou, Qiuting Huang, Luca Benini
Pubblicato in: IEEE Transactions on Parallel and Distributed Systems, Numero 10459219, 2021, Pagina/e 633-648, ISSN 1045-9219
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2020.3028691

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes

Autori: Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti; Luca Benini; Davide Rossi
Pubblicato in: IEEE Transactions on Emerging Topics in Computing, Numero 21686750, 2021, Pagina/e 1489 - 1505, ISSN 2168-6750
Editore: IEEE Computer Society
DOI: 10.1109/tetc.2021.3072337

A hardware/software co-design vision for deep learning at the edge

Autori: Flavio Ponzina, Simone Machetti, Marco Antonio Rios, Benoît Walter Denkinger, Alexandre Sébastien Julien Levisse, Giovanni Ansaloni, Miguel Peon Quiros, and David Atienza
Pubblicato in: IEEE Micro, Numero 02721732, 2022, Pagina/e 48-54, ISSN 0272-1732
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/mm.2022.3195617

Terahertz Rectennas on Flexible Substrates Based on One-Dimensional Metal–Insulator–Graphene Diodes

Autori: Andreas Hemmeter; Xinxin Yang; Zhenxing Wang; Martin Otto; Burkay Uzlu; Marcel Andree; Ullrich R. Pfeiffer; Andrei Vorobiev; Jan Stake; Max C. Lemme; Daniel Neumaier
Pubblicato in: ACS Applied Electronic Materials, Numero 26376113, 2021, ISSN 2637-6113
Editore: ACS
DOI: 10.18154/rwth-2021-09071

BLADE: An in-Cache Computing Architecture for Edge Devices

Autori: William Andrew Simon, Yasir Mahmood Qureshi, Marco Rios, Alexandre Levisse, Marina Zapater, David Atienza
Pubblicato in: IEEE Transactions on Computers, Numero 69/9, 2020, Pagina/e 1349-1363, ISSN 0018-9340
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2020.2972528

Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning

Autori: Theresia Knobloch; Burkay Uzlu; Yury Yu. Illarionov; Zhenxing Wang; Martin Otto; Lado Filipovic; Michael Waltl; Daniel Neumaier; Max C. Lemme; Tibor Grasser
Pubblicato in: Nature Electronics, Numero 25201131, 2022, Pagina/e 356-366, ISSN 2520-1131
Editore: Nature
DOI: 10.1038/s41928-022-00768-0

Genome sequence alignment - Design space exploration for optimal performance and energy architectures

Autori: Yasir Mahmood Qureshi, Jose Manuel Herruzo, Marina Zapater, Katzalin Olcoz, Sonia Gonzalez-Navarro, Oscar Plata, David Atienza
Pubblicato in: IEEE Transactions on Computers, Numero 00189340, 2021, Pagina/e 2218-2233, ISSN 0018-9340
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2020.3041402

Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

Autori: Najibi, Halima, Alexandre Sébastien Julien Levisse, Giovanni Ansaloni, Marina Zapater Sancho, Miroslav Vasic, and David Atienza Alonso
Pubblicato in: Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numero 02780070, 2022, ISSN 0278-0070
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2022.3168257

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Autori: Angelo Garofalo; Francesco Conti; DAVIDE ROSSI; Giuseppe Tagliavini; GIANMARCO OTTAVI; LUCA BENINI; Alfio Di Mauro
Pubblicato in: IEEE Transactions on Circuits and Systems 2023, Numero 6, 2023, Pagina/e 2450 - 2463, ISSN 1558-0806
Editore: IEEE
DOI: 10.1109/tcsi.2023.3254810

A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks

Autori: Angelo Garofalo; Geethan Karunaratne; Francesco Conti; DAVIDE ROSSI; Irem Boybat; GIANMARCO OTTAVI; LUCA BENINI
Pubblicato in: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Numero 21563357, 2022, Pagina/e 422-435, ISSN 2156-3357
Editore: IEEE Circuits and Systems Society
DOI: 10.1109/jetcas.2022.3170152

Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Manycores

Autori: Antonio Franques; Sergi Abadal; Haitham Hassanieh; Josep Torrellas
Pubblicato in: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, Pagina/e 1657-1662
Editore: IEEE
DOI: 10.23919/date51398.2021.9473960

Characterizing the Communication Requirements of GNN Accelerators: A Model-Based Approach

Autori: Robert Guirado; Akshay Jain; Sergi Abadal; Eduard Alarcón
Pubblicato in: IEEE International Symposium on Circuits and Systems 2021, 2021, ISBN 978-1-7281-9201-7
Editore: IEEE
DOI: 10.1109/iscas51556.2021.9401612

RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs

Autori: Tortorella, Yvan; Bertaccini, Luca; Rossi, Davide; Benini, Luca; Conti, Francesco
Pubblicato in: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, Pagina/e 1099-1102
Editore: IEEE
DOI: 10.23919/date54114.2022.9774759

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

Autori: Davide Rossi; Francesco Conti; Manuel Eggiman; Stefan Mach; Alfio Di Mauro; Marco Guermandi; Giuseppe Tagliavini; Antonio Pullini; Igor Loi; Jie Chen; Eric Flamand; Luca Benini
Pubblicato in: 2021 IEEE International Solid-State Circuits Conference (ISSCC), 2021, Pagina/e 60-62
Editore: IEEE
DOI: 10.1109/isscc42613.2021.9365939

Understanding the Impact of On-chip Communication on DNN Accelerator Performance

Autori: Robert Guirado, Hyoukjun Kwon, Eduard Alarcon, Sergi Abadal, Tushar Krishna
Pubblicato in: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019, Pagina/e 85-88, ISBN 978-1-7281-0996-1
Editore: IEEE
DOI: 10.1109/icecs46596.2019.8964858

Multi-channel Medium Access Control Protocols for Wireless Networks within Computing Packages

Autori: Bernat Ollé; Pau Talarn; Albert Cabellos-Aparicio; Filip Lemic; Eduard Alarcón; Sergi Abadal
Pubblicato in: IEEE International Symposium on Circuits and Systems 2023, Numero 17, 2023
Editore: IEEE
DOI: 10.1109/iscas46773.2023.10182198

Enabling mixed-precision quantized neural networks in extreme-edge devices

Autori: Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
Pubblicato in: Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020, Pagina/e 217-220, ISBN 9781450379564
Editore: ACM
DOI: 10.1145/3387902.3394038

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

Autori: Rios, Marco, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, and David Atienza
Pubblicato in: Proceedings of the Great Lakes Symposium on VLSI, 2022, Pagina/e 249-254
Editore: IEEE
DOI: 10.1145/3526241.3530351

GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors

Autori: Bruschi, Nazareno; Haugou, Germain; Tagliavini, Giuseppe; Conti, Francesco; Benini, Luca; Rossi, Davide
Pubblicato in: 2021 IEEE 39th International Conference on Computer Design (ICCD), 2021, Pagina/e 409-416
Editore: IEEE
DOI: 10.1109/iccd53106.2021.00071

Towards spatial multiplexing in wireless networks within computing packages

Autori: Fátima Rodríguez-Galán, Elana Pereira de Santana, Peter Haring Bolívar, Sergi Abadal, Eduard Alarcón
Pubblicato in: NANOCOM '22: Proceedings of the 9th ACM International Conference on Nanoscale Computing and Communication, 2022, Pagina/e Art. 21, ISBN 978-1-4503-9867-1
Editore: Association for Computing Machinery
DOI: 10.1145/3558583.3558875

Tunable Plasmonic Graphene Antenna Array for Communications at THz Frequencies

Autori: Elana P. De Santana, Daniel Stock, Zhenxing Wang, Kun-Ta Wang, Sergi Abadal, Max Lemme, Peter H. Bolívar
Pubblicato in: 48th International Conference on Infrared, Millimeter and Terahertz Waves 2023, 2023, ISBN 979-8-3503-3660-3
Editore: IEEE
DOI: 10.1109/irmmw-thz57677.2023.10299218

An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs

Autori: Ponzina, Flavio, Miguel Peon-Quiros, Giovanni Ansaloni, and David Atienza
Pubblicato in: International Conference on Omni-layer Intelligent Systems (COINS), 2022, ISBN 978-1-6654-8357-5
Editore: IEEE
DOI: 10.1109/coins54846.2022.9854986

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

Autori: Amirshahi, Alireza; Klein, Joshua Alexander Harrison; Ansaloni, Giovanni; Atienza Alonso, David
Pubblicato in: 8th Asia and South Pacific Design Automation Conference 2023, 2023, ISBN 978-1-4503-9783-4
Editore: ACM
DOI: 10.1145/3566097.3567867

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing

Autori: Rios, Marco Antonio ; Ponzina, Flavio ; Ansaloni, Giovanni ; Levisse, Alexandre Sébastien Julien ; Atienza Alonso, David
Pubblicato in: Design, Automation and Test in Europe Conference, Virtual Conference and Exhibition (DATE), 2021
Editore: IEEE/ACM
DOI: 10.23919/date51398.2021.9474233

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

Autori: Medina, Rafael, Joshua Kein, Yasir Qureshi, Marina Zapater, Giovanni Ansaloni, and David Atienza
Pubblicato in: Latin America Symposium on Circuits and System (LASCAS), 2022
Editore: IEEE
DOI: 10.1109/lascas53948.2022.9893905

WiDir: A Wireless-Enabled Directory Cache Coherence Protocol

Autori: Antonio Franques; Apostolos Kokolis; Sergi Abadal; Vimuth Fernando; Sasa Misailovic; Josep Torrellas
Pubblicato in: 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2021, Pagina/e 304-317
Editore: IEEE
DOI: 10.1109/hpca51647.2021.00034

Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays.

Autori: Najibi, Halima, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, and David Atienza
Pubblicato in: Great Lakes Symposium on VLSI, 2022, Pagina/e 223-228
Editore: IEEE
DOI: 10.1145/3526241.3530309

Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package

Autori: Robert Guirado; Hyoukjun Kwon; Sergi Abadal; Eduard Alarcon; Tushar Krishna
Pubblicato in: 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 2021, Pagina/e 806-812
Editore: IEEE
DOI: 10.48550/arxiv.2011.14755

REMOTE: Re-thinking Task Mapping on Wireless 2.5 D Systems-on-Package for Hotspot Removal

Autori: Medina Morillas, Rafael ; Huang, Darong ; Ansaloni, Giovanni ; Zapater Sancho, Marina ; Atienza Alonso, David
Pubblicato in: IFIP/IEEE 31st International Conference on Very Large Scale Integration 2023, 2023
Editore: IEEE
DOI: 10.1109/vlsi-soc57769.2023.10321912

System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms

Autori: Rafael Medina, Joshua Kein, Giovanni Ansaloni, Marina Zapater, Sergi Abadal, Eduard Alarcón, David Atienza
Pubblicato in: 28th Asia and South Pacific Design Automation Conference 2023, 2023
Editore: ACM
DOI: 10.1145/3566097.3567952

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

Autori: Halima Najibi, Jorge Hunter, Alexandre Levisse, Marina Zapater, Miroslav Vasic, David Atienza
Pubblicato in: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, Pagina/e 18-23, ISBN 978-1-7281-5775-7
Editore: IEEE
DOI: 10.1109/isvlsi49217.2020.00014

A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Autori: Angelo Garofalo; Gianmarco Ottavi; Alfio Di Mauro; Francesco Conti; Giuseppe Tagliavini; Luca Benini; Davide Rossi
Pubblicato in: IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, Pagina/e 267-270
Editore: IEEE
DOI: 10.1109/esscirc53450.2021.9567767

An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes

Autori: Hayate Okuhara; Ahmed Elnaqib; Davide Rossi; Alfio Di Mauro; Philipp Mayer; Pierpaolo Palestri; Luca Benini
Pubblicato in: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020
Editore: IEEE
DOI: 10.1109/iscas45731.2020.9181081

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Autori: Halima Najibi, Alexandre Levisse, Marina Zapater, Mohamed M. Sabry Aly, David Atienza
Pubblicato in: Proceedings of the 2020 on Great Lakes Symposium on VLSI, 2020, Pagina/e 513-518, ISBN 9781450379441
Editore: ACM
DOI: 10.1145/3386263.3406923

Collective Communication Patterns Using Time-Reversal Terahertz Links at the Chip Scale

Autori: Fátima Rodríguez-Galán, Ama Bandara, Elana Pereira de Santana, Peter Haring Bolívar, Eduard Alarcón, Sergi Abadal
Pubblicato in: IEEE Global Communications Conference 2023, 2023
Editore: IEEE
DOI: 10.48550/arxiv.2309.01428

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

Autori: Alexandre Levisse, Marco Rios, Miguel Peon-Quiros, David Atienza
Pubblicato in: ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2020, Pagina/e 1549-1552, ISBN 978-1-5090-6631-5
Editore: IEEE
DOI: 10.1109/icassp40776.2020.9054524

Exploration of Time Reversal for Wireless Communications within Computing Packages

Autori: Ama Bandara; Fátima Rodríguez-Galán; Elana Pereira de Santana; Peter Haring Bolívar; Eduard Alarcón; Sergi Abadal
Pubblicato in: 10th ACM International Conference on Nanoscale Computing and Communication 2023, Numero 13, 2023
Editore: ACM
DOI: 10.1145/3576781.3608723

End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet?.

Autori: Gianmarco Ottavi; Geethan Karunaratne; Francesco Conti; Irem Boybat; Luca Benini; Davide Rossi
Pubblicato in: 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021, Pagina/e 1-4
Editore: IEEE
DOI: 10.1109/aicas51828.2021.9458409

Toward Dynamically Adapting Wireless Intra-Chip Channels to Traffic Needs with a Programmable Metasurface

Autori: Mohammadreza F. Imani; Sergi Abadal; Philipp del Hougne
Pubblicato in: Proceedings of the 1st ACM International Workshop on Nanoscale Computing, Communication, and Applications, 2020
Editore: ACM
DOI: 10.1145/3416006.3431274

Validating Full-System RISC-V Simulator: A Systematic Approach

Autori: Pathak, Karan ; Klein, Joshua Alexander Harrison ; Ansaloni, Giovanni ; Zapater Sancho, Marina ; Atienza Alonso, David
Pubblicato in: RISC-V Summit Europe 2023, 2023, Pagina/e 2
Editore: RISC-V

A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference

Autori: Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
Pubblicato in: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, Pagina/e 512-517, ISBN 978-1-7281-5775-7
Editore: IEEE
DOI: 10.1109/isvlsi49217.2020.000-5

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance.

Autori: Simon, William Andrew, Alexandre Levisse, Marina Zapater, and David Atienza
Pubblicato in: 28th International Conference on Very Large Scale Integration (VLSI-SOC), 2020, Pagina/e 94-99, ISBN 978-1-7281-5410-7
Editore: IEEE
DOI: 10.1109/vlsi-soc46417.2020.9344087

End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture

Autori: Nazareno Bruschi; Giuseppe Tagliavini; Angelo Garofalo; Francesco Conti; Irem Boybat; Luca Benini; Davide Rossi
Pubblicato in: IEEE Design, Automation & Test in Europe Conference & Exhibition 2023, Numero 11, 2023, ISSN 1558-1101
Editore: IEEE
DOI: 10.23919/date56975.2023.10137208

Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing

Autori: Robert Guirado, Abbas Rahimi, Geethan Karunaratne, Eduard Alarcón, Abu Sebastian, Sergi Abadal
Pubblicato in: 2022 IEEE International Joint Conference on Neural Networks (IJCNN), 2022, ISBN 978-1-7281-8671-9
Editore: IEEE
DOI: 10.1109/ijcnn55064.2022.9892243

Integrated Graphene Patch Antenna for Communications at THz Frequencies

Autori: E. P. de Santana, A. K. Wigger, Z. Wang, K. Wang, M. Lemme, S. Abadal, P. H. Bolivar
Pubblicato in: 2022 47th International Conference on Infrared, Millimeter and Terahertz Waves (IRMMW-THz), 2022, ISBN 978-1-7281-9427-1
Editore: IEEE
DOI: 10.1109/irmmw-thz50927.2022.9895979

Characterizing the Communication Requirements of GNN Accelerators: A Model-Based Approach

Autori: Robert Guirado; Akshay Jain; Sergi Abadal; Eduard Alarcon
Pubblicato in: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, Pagina/e 1-5
Editore: IEEE
DOI: 10.48550/arxiv.2103.10515

Scale up your in-memory accelerator: leveraging wireless-on-chip communication for aimc-based cnn inference

Autori: Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti, Sergi Abadal, Alberto Cabellos-Aparicio, Eduard Alarcon, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
Pubblicato in: 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, ISBN 978-1-6654-0996-4
Editore: IEEE
DOI: 10.1109/aicas54282.2022.9869996

wireless plasticity for massive heterogeneous computer architectures (WiPLASH)

Autori: Joshua Klein; Alexandre Levisse; Giovanni Ansaloni; David Atienza; Marina Zapater; Martino Dazzi; Geethan Karunaratne; Irem Boybat; Abu Sebastian; Davide Rossi; Francesco Conti; Elana Pereira de Santana; Peter Haring Bolívar; Mohamed Saeed; Renato Negra; Zhenxing Wang; Kun-Ta Wang; Max C. Lemme; Akshay Jain; Robert Guirado; Hamidreza Taghvaee; Sergi Abadal
Pubblicato in: ACM Computing Frontiers, 2021
Editore: ACM
DOI: 10.1145/3457388.3458859

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Architecting More Than Moore – Wireless Plasticity for Heterogeneous Massive Computer Architectures

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