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High-Density IC Card


The objective of the project is the development of a new generation of smart cards, which will combine high density non volatile memory technology with state of the art computer architectures and advanced security features, based on public key algorithms.

An innovative EEPROM memory cell will be developed, based on ST's current flash memory technology, which will offer a density 2/4 time better than current state-of-the-art EEPROM processes, while keeping the same low power dissipation. A programming time in the range of 1 ms and a cell size of about 12 micron{2} are targeted for the final technology implementation in 0.6 micron technology. Cell size will be compatible with the realisation of 1 Mb EEPROM embedded blocks.

The smartcard will present the following features:

- single power supply, down to less than 2.5 V
- very low power consumption sleep mode
- high-speed data rate (> 100 Kbit/s), achieved with the use of a SRAM buffer and parallel writing of NVM
- enhanced security features, based on a public key algorithm, with key length up to 1024 bit
- a coprocessor able to perform exponentiation in about 0.5sec at a clock rate of 3.57 MHz
- small chip area (<15 mm{2}).

The new cell architecture will be first demonstrated in 0.8 micron technology on a 256 K stand-alone memory in the first year of the project. This memory will be used to qualify the memory cell technology and to identify all possible reliability hazards. A device shrink to 0.6 micron design rules will be made possible by the use of special "shrinkable" rules in the first design phase.

Development of critical process steps and investigation on cell reliability and intrinsic cell security will be carried out in parallel, with the help of two research institutions (NMRC in Ireland and EPFL in Switzerland).

A new operating system will be developed to manage the large embedded memory and the more powerful security features, based on public key algorithm.

Prototyping of the 0.6 micron technology smartcard is scheduled for 1995, while full product validation is expected in 1996, at the end of the project. The project will include card fabrication, and validation of the full system on a typical application.

At present, a device with 64 Kbit of embedded EEPROM and a public key algorithm is foreseen as the demonstrator of the new smartcard technology. However, market developments will be constantly monitored and the results taken account of in the project.


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Call for proposal

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Funding Scheme

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SGS-Thomson Microelectronics SrL
EU contribution
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20041 Agrate Brianza (MI)

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Participants (4)