Periodic Reporting for period 1 - PROMISE (PROgrammable MIxed Signal Electronics)
Período documentado: 2020-01-01 hasta 2021-12-31
With the rise of NewSpace, the space market is undergoing a mutation that promotes integration/miniaturization, satellite acceleration, cost-efficient and cost-reduction options for all mission types, including robotic exploration, science, Earth observation, communications and navigation. The high performance/high capacity FPGA, new multicore devices, Rad Tolerant components, and COTS are in competition with middle range ASIC solutions as a result. In fact, Mixed Signal ASIC solutions provide functional value addition for electronic unit testability and full analog function digitization. As a result, the PROMISE project establishes precise, quantifiable goals to reduce risks in analog and mixed ASIC radhard design, manufacturing and qualification while maximizing design cost and schedule.
In more detail, PROMISE is intended to give the space community access to a flexible mixed signal ASIC architecture design environment that is based on a variety of robust features. A modular mixed signal ASIC manufacturing and qualification ecosystem will also be made available by the project. Last but not least, PROMISE will provide IP management, commercialization and distribution to enable effective reuse of project achievements and a productive environment for new IPs and mid-range ASIC design for space applications.
Leading members of the European Mixed Signal ASIC ecosystem are included in PROMISE which is led by Thales Alenia Space and includes a variety of European partners, subcontractors, potential customers and solution providers. Mega constellation sales are booming and numerous projects supported by various operators are already under way. A 50% market share will be attained as a result of PROMISE and over 700 satellites are expected to be delivered over the course of the next 5 to 10 years. If each constellation only has one PROMISE-based ASIC and each satellite has at least four of them more than 2800 units would be provided in the first five years following the project.
In more detail, PROMISE is intended to give the space community access to a flexible mixed signal ASIC architecture design environment that is based on a variety of robust features. A modular mixed signal ASIC manufacturing and qualification ecosystem will also be made available by the project. Last but not least, PROMISE will provide IP management, commercialization and distribution to enable effective reuse of project achievements and a productive environment for new IPs and mid-range ASIC design for space applications.
Leading members of the European Mixed Signal ASIC ecosystem are included in PROMISE which is led by Thales Alenia Space and includes a variety of European partners, subcontractors, potential customers and solution providers. Mega constellation sales are booming and numerous projects supported by various operators are already under way. A 50% market share will be attained as a result of PROMISE and over 700 satellites are expected to be delivered over the course of the next 5 to 10 years. If each constellation only has one PROMISE-based ASIC and each satellite has at least four of them more than 2800 units would be provided in the first five years following the project.
In this reporting period the specification for all PROMISE IPs (11) were issued including the specs for Standard cells, IOs, Bandgap, Local Oscillator, ADC, DAC, PLL, LDO, Power On Reset, Non Volatile Memory, eFPGA and HVMOS. Moreover, the Consortium prepared and issued the specification for the PROMISE Pilot Circuit. All these were submitted to the European Commission as per the Grant Agreement.
To support a unified IP design process and IP data package format inside the consortium which would also be of use for future comers, a Design Standard document and an Interface Standard document, including its related checklist, were issued and delivered.
Design of the eFPGA, the biggest IP in PROMISE, has been successfully completed by MENTA. ISD completed the design of the Low Drop Out IP whereas IMEC completed the Standard cells and IOs designs consisting of an upgrade of the existing DARE180XH library. All data packages were checked and delivered successfully to the PROMISE IP repository at IMEC.
The design of all other IPs were conducted almost up to DDR before the end of the period in December 2021. For the NVM, IMEC were forced to reconsider 100% of the initial design hypothesis (based on hardening of the existing XFAB NVM) and the Consortium proposed the 2nd amendment to the GA in order to allow a full re-design of the NVM from scratch based on the unitary bit cell from the XFAB library. Despite this huge challenge, IMEC was able to execute the design phases up to the DDR.
The Front-end and back-end design of the Pilot Circuit were executed up to the DDR.
To support qualification and manufacturing of the Pilot Circuit and future ASIC designed in PROMISE eco-system, a Qualification plan standard document and a Manufacturing Plan Standard document were issued and delivered. Those documents were also used to conduct a survey to identify capabilities of all European potential supply chain actors covering manufacturing, test and qualification ; the survey results are gathered in a Supplier selection guide available for the PROMISE community. The suppliers short list for the Pilot Circuit were identified and SERMA France was finally selected. The final package strategy for the Pilot Circuit is defined : chip-on-board will be used for testing. Preliminary version of the Pilot Circuit validation plan were issued.
A first Core Users Group session were successfully organized to extend the PROMISE eco system. Most of the space community actors were represented and the Consortium obtained a positive feedback from the participants. The Core Users Group gathered experts from European and national agencies, satellite industry, design houses, research institutes, etc… A second session is planned for next period.
On top of technical activities, the Consortium set up PROMISE webpage : https://promise-h2020.eu/. Several news articles were added following the rhythm of the IP design CDRs in order to inform the community about the progress and achievements made in PROMISE.
Finally, the project coordination was successful on both technical and organizational aspects having as a result a group of experts from 7 European institutions working together towards their common goal, an all European mixed-signal ASIC for space applications.
To support a unified IP design process and IP data package format inside the consortium which would also be of use for future comers, a Design Standard document and an Interface Standard document, including its related checklist, were issued and delivered.
Design of the eFPGA, the biggest IP in PROMISE, has been successfully completed by MENTA. ISD completed the design of the Low Drop Out IP whereas IMEC completed the Standard cells and IOs designs consisting of an upgrade of the existing DARE180XH library. All data packages were checked and delivered successfully to the PROMISE IP repository at IMEC.
The design of all other IPs were conducted almost up to DDR before the end of the period in December 2021. For the NVM, IMEC were forced to reconsider 100% of the initial design hypothesis (based on hardening of the existing XFAB NVM) and the Consortium proposed the 2nd amendment to the GA in order to allow a full re-design of the NVM from scratch based on the unitary bit cell from the XFAB library. Despite this huge challenge, IMEC was able to execute the design phases up to the DDR.
The Front-end and back-end design of the Pilot Circuit were executed up to the DDR.
To support qualification and manufacturing of the Pilot Circuit and future ASIC designed in PROMISE eco-system, a Qualification plan standard document and a Manufacturing Plan Standard document were issued and delivered. Those documents were also used to conduct a survey to identify capabilities of all European potential supply chain actors covering manufacturing, test and qualification ; the survey results are gathered in a Supplier selection guide available for the PROMISE community. The suppliers short list for the Pilot Circuit were identified and SERMA France was finally selected. The final package strategy for the Pilot Circuit is defined : chip-on-board will be used for testing. Preliminary version of the Pilot Circuit validation plan were issued.
A first Core Users Group session were successfully organized to extend the PROMISE eco system. Most of the space community actors were represented and the Consortium obtained a positive feedback from the participants. The Core Users Group gathered experts from European and national agencies, satellite industry, design houses, research institutes, etc… A second session is planned for next period.
On top of technical activities, the Consortium set up PROMISE webpage : https://promise-h2020.eu/. Several news articles were added following the rhythm of the IP design CDRs in order to inform the community about the progress and achievements made in PROMISE.
Finally, the project coordination was successful on both technical and organizational aspects having as a result a group of experts from 7 European institutions working together towards their common goal, an all European mixed-signal ASIC for space applications.
First challenge was to define a modular and flexible architecture covering the needs of Mixed-Signal ASIC : MENTA contributed to this challenge by designing the hardened eFPGA core ; it will provide flexibility in future ASIC implemented in the PROMISE technology. IMEC designed the NVM up to DDR by implementing innovative configuration and tuning capabilities that will drastically improve the NVM validation tests and manufacturing tests.
Second challenge was to establish a complete Mixed-Signal ASIC Supply Chain defining all its actors, production steps and the interfaces between each of them : a Supplier selection guide is now available to support space community to efficiently select their ASIC supply chain.
Third challenge was to succeed in hardening of the most challenging IPs : thanks to the improved DARE180XH library and specific hardened cells, the eFPGA hardening by design was successfully done. Hardening of the other IPs were mainly done using the SET Striker tool from IMEC at schematic level ; at DDR stage, all IPs are showing high level of SET immunity. TID hardened version of high voltage NMOS transistors were designed.
The fourth challenge was to overcome technical complexity to design a mixed-signal ASIC, the Pilot Circuit, embedding IPs from different providers while keeping their electrical and radiation performances : different partners were using the Design Standard document and the Interface Standard document to ensure overall IPs consistency and allow a fluent integration in Pilot Circuit. Despite schedule challenge and all IP design in parallel with different design stage, it was possible to anticipate the IPs integration in the Pilot Circuit front-end and back-end design.
The fifth challenge was to establish an active community of PROMISE users and foster the adoption of the PROMISE technology amongst the Space Community : the success of the first PROMISE Core Users Group demonstrates the interest of the space community and several stakeholders have expressed interest in being invited for the second session scheduled for the next period.
Second challenge was to establish a complete Mixed-Signal ASIC Supply Chain defining all its actors, production steps and the interfaces between each of them : a Supplier selection guide is now available to support space community to efficiently select their ASIC supply chain.
Third challenge was to succeed in hardening of the most challenging IPs : thanks to the improved DARE180XH library and specific hardened cells, the eFPGA hardening by design was successfully done. Hardening of the other IPs were mainly done using the SET Striker tool from IMEC at schematic level ; at DDR stage, all IPs are showing high level of SET immunity. TID hardened version of high voltage NMOS transistors were designed.
The fourth challenge was to overcome technical complexity to design a mixed-signal ASIC, the Pilot Circuit, embedding IPs from different providers while keeping their electrical and radiation performances : different partners were using the Design Standard document and the Interface Standard document to ensure overall IPs consistency and allow a fluent integration in Pilot Circuit. Despite schedule challenge and all IP design in parallel with different design stage, it was possible to anticipate the IPs integration in the Pilot Circuit front-end and back-end design.
The fifth challenge was to establish an active community of PROMISE users and foster the adoption of the PROMISE technology amongst the Space Community : the success of the first PROMISE Core Users Group demonstrates the interest of the space community and several stakeholders have expressed interest in being invited for the second session scheduled for the next period.