The MORAL project has achieved excellent technical and non-technical progress over the course of its 49 months. The complete PEAKTOP ISA and corresponding RTL model of the processor were developed and verified in simulation. Performance and capabilities improvements of the base PEAKTOP were carried out by re-designing the MPU and the design of the FPU unit. All planned peripherals were integrated into the processor core, including the PWM generator, Watchdog timer, Pulse counter, CAN 2.0 module, SpaceWire, MIL-STD 1553C, SPI, I2C, and UART interfaces.
The design and verification using modern techniques were initially demonstrated with the PEAKTOP processor and carried on to the MORAL chip design flow. The co-verification, simulation, and testing platform used in MORAL has the advantage of parallel hardware and software design and verification. The reports generated by the platform provide extensive information about the hardware and software behavior, which is further used to identify possible inefficiencies and bottlenecks. Verification and integration tests were executed at every design step, from RTL simulations to post-synthesis, FPGA emulation of the MORAL core and digital peripherals, and, at last, post-layout.
Even though the project's roadmap didn't include the FPGA emulation at first, the decision to have it was of utmost importance for the core verification and the early tests of the ported C-compiler and early RTSK (real-time separation kernel) development for the target PEAKTOP architecture. The compiler development, which includes the binary utilities, was completed, and an extensive debugging phase was conducted. The RTSK targeting a small footprint memory was specified. The preliminary RSTK implementation was tested in the FPGA platform. Later on, the RTSK needs for the target applications were developed and tested in the demonstrator platform.
The project radiation protection relies on high-level methods, such as ECC for memory, HDL coding style for high reliability, and the use of the TMR (triple modular redundancy) approach. The processor core was synthesized targeting The radiation-hard standard-cell library SG13RH. The layout phase of the entire core and other preparations for its fabrication was completed, and the chip was submitted for fabrication. However, other four chips were fabricated during the project: a chip including the SRAM blocks, a chip with the 10-bit DAC that was later upgraded to the final 12-bit version, and a chip with the 12-bit ADC. was developed, manufactured, and passed the tests with packaged chips. The DAC was preliminary tested under Cobalt-60 and successfully demonstrated its robustness to radiation environments.
After the MORAL chips fabrication, they went through the wafer test phase, and the working units were selected for packaging. PCBs for the package tests, stress tests, and demonstrator platform were designed, fabricated, and later assembled. Several test cases were developed for the functional and radiation tests and also for the electrical and performance measurements. Once the packaged chips were available, the stress and life tests were conducted. All tests were completed, and based on the test results, the MORAL microcontroller is suitable for any space mission orbit and duration.
Dissemination activities included creating a preliminary exploitation plan that was later reviewed and extended into the final exploitation plan and a business plan to introduce the MORAL chip into the market. The project website concentrated the relevant information on the project. Along with the website, the project's LinkedIn page and YouTube channel were used for the dissemination activities. After the strong technical development phase that took place it was possible to increase the project dissemination based on the technical results. These include some scientific papers and presentations in important events, such as AMICSA'22 and the European Space Week 2022, as well as the organizing of the workshop called "Fault-tolerant Electronics for Radiation Environments."
