This project aims to develop strategies which increase the functional test capabilities of systems based on mixed-signal integrated circuits using features presently available for digital circuits. Test during the system operational life and/or self-checking will be introduced. Demonstrators corresponding to potentially critical applications will be realised. To combine these new features in an effective manner, compatible Design For Testability techniques (DFT) as well as practical off-line test generation strategies, will also be developed.
APPROACH AND METHODS
The research work is focused along four main directions (on-line testability, self-checking, DFT and off-line test generation) that will interact among themselves and lead the design of demonstrators which incorporate the concepts developed.
This project involves both design and test, and requires analog and digital expertise. Participants have been selected with experience in design (at cell and systems levels), design for testability, test pattern generation, input/output testing, IDD test methods, and concurrent test. The partners within the consortium cover all these aspects, bringing their specific and complementary expertise to cooperate in a multidisciplinary approach to cope with the difficulty of advancing the field of testing mixed-signal integrated circuits.
AMATIST is expected to advance the state of the art by a) introducing methodologies and circuit architectures for functional on-line monitoring of mixed-signal circuits and boards; b) creating DFT strategies which can be used to test (off-line) those systems designed using the mentioned methodologies; c) developing efficient procedures and software CAD tools for the generation of off-line tests which can be used with circuits designed following the new methodologies; d) exploring the applicability of power supply current tests; and e) making these design and test methodologies available to European industries that fabricate or use mixed-signal chips in complex microelectronics systems.
Expected results are foreseen to impact three areas: 1) reduction in time-to market of integrated systems, because applying on-line test during the product field operation will alleviate the production test requirements, 2) increasing the overall systems reliability, since fault occurrence is immediately detected, and 3) decreasing both maintenance cost and unavailability time. Improving performance at a lower cost is essential for silicon manufacturers.