Periodic Reporting for period 1 - H-3D-SOC (3D IC Design Flow for Hybrid-bonding 3D System on Chip)
Reporting period: 2020-04-01 to 2022-03-31
Development of design methods & practical tools for a face-to-face and wafer by wafer hybrid bonding based H-3D-SOC is explored to optimize the performance and benefits of the 3D system for multi-core in-parallel processor application. Furthermore, to quantitatively evaluate the impact of process variation on the performance and reliability of H-3D-SOC IC, the variability and reliability models for hybrid bonding pads will first be developed and calibrated by experimental measurement such as daisy chain conducted by the IMEC 3D process group. Then, the hybrid bonding pad models will be applied to dynamically evaluate the performance of H-3D-SOC under specific testbenches and predict the 3D system time-to-failure by referring to the 2D counterpart performance. Finally, to mitigate the impact of hybrid bonding process variation on system performance and reliability, the critical pads will be efficiently identified and hardened by adding a spare hybrid bonding pad to each of the critical pad.
The implementation of H-3D-SOC provided the research and technical groundwork to address a two-fold innovation goal:
Design enablement of face-to-face 3D IC with nominal hybrid-bonding vertical interconnects.
Hardening technique to improve variability and reliability of the H-3D-SOC.
Over these 18 months of the project, H-3D-SOC has achieved most of its key research goals as well as the training and public outreach goals that have been set. In view of the early termination of the project, due to family/professional reasons of the MSCA fellow, the status of the work related to the second goal has not been completed yet due to the limit or lag of EDA tool support for this work; the fellow will commit to working on this once the EDA tool is ready. However, the fellow has updated this goal with another interesting study which is also highly related to the H-3D-SOC project: 3D optimized SRAM macro design, optimization and its application to the memory-on-logic 3D system.
In order to best align the above goals of H-3D-SOC with emerging R&D challenges and needs in the semiconducting industry, the overall research plan carried out in the project was particularly adapted and focused on the following activities-objectives:
1. Propose the 3D die-by-die flow based on 3D hybrid bonding technology. The 3D hybrid bonding technology was characterized and modeled based on experimental tests.
2. Proposed 3D optimized SRAM macro by optimizing the pin locations of the macro for better 3D Place and Route PPAC (power-performance-area-cost).
3. Demonstrated 3D memory-on-logic exploration based on the proposed 3D technology and optimized 3D macro
The implementation of H-3D-SOC provided the research and technical groundwork to address a two-fold innovation goal:
Design enablement of face-to-face 3D IC with nominal hybrid-bonding vertical interconnects.
Hardening technique to improve variability and reliability of the H-3D-SOC.
Over these 18 months of the project, H-3D-SOC has achieved most of its key research goals as well as the training and public outreach goals that have been set. In view of the early termination of the project, due to family/professional reasons of the MSCA fellow, the status of the work related to the second goal has not been completed yet due to the limit or lag of EDA tool support for this work; the fellow will commit to working on this once the EDA tool is ready. However, the fellow has updated this goal with another interesting study which is also highly related to the H-3D-SOC project: 3D optimized SRAM macro design, optimization and its application to the memory-on-logic 3D system.
In order to best align the above goals of H-3D-SOC with emerging R&D challenges and needs in the semiconducting industry, the overall research plan carried out in the project was particularly adapted and focused on the following activities-objectives:
1. Propose the 3D die-by-die flow based on 3D hybrid bonding technology. The 3D hybrid bonding technology was characterized and modeled based on experimental tests.
2. Proposed 3D optimized SRAM macro by optimizing the pin locations of the macro for better 3D Place and Route PPAC (power-performance-area-cost).
3. Demonstrated 3D memory-on-logic exploration based on the proposed 3D technology and optimized 3D macro
The work in WP1 was mainly related to the multi-core 3D partitioning and PPAC evaluation compared with a 2D counterpart. As shown in Fig. 1, a multicore SoC was first partitioned through the EDA tool supported by Cadence. The target 50%-50% area split was achieved to fully optimized the area improvement benefit of 3D SoC. Furthermore, the interconnect wire length saving was obtained to show the potential reduction in SoC power from the interconnect.
Based on the work of WP1, a 3D optimized SRAM macro was proposed to further reduce the 3D macro wirelength in the global routing and hence the 3D SoC system at the end. This is to replace the work originally to be done in WP2. Further on, a solution to improve the 3D SoC system was proposed by combining the WP1 and WP2 to compose the updated WP3, namely a 3D optimized SoC system with partitioned memory and logic + optimized SRAM macro.
Based on the work of WP1, a 3D optimized SRAM macro was proposed to further reduce the 3D macro wirelength in the global routing and hence the 3D SoC system at the end. This is to replace the work originally to be done in WP2. Further on, a solution to improve the 3D SoC system was proposed by combining the WP1 and WP2 to compose the updated WP3, namely a 3D optimized SoC system with partitioned memory and logic + optimized SRAM macro.
Through the aforementioned work progress and innovation activities, there were three main results beyond the state of the art:
For the first time, multicore SoC was partitioned using die-by-die flow with imec state-of-the-art hybrid bonding technology.
3D optimized SRAM macro was proposed for the first time and evaluated at a imec advanced technologies from 5nm to 3nm.
Combined 3D optimized SRAM macro and partitioned memory-on-logic to double boost the system multi-core SoC PPAC.
For the first time, multicore SoC was partitioned using die-by-die flow with imec state-of-the-art hybrid bonding technology.
3D optimized SRAM macro was proposed for the first time and evaluated at a imec advanced technologies from 5nm to 3nm.
Combined 3D optimized SRAM macro and partitioned memory-on-logic to double boost the system multi-core SoC PPAC.