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3D IC Design Flow for Hybrid-bonding 3D System on Chip

Project description

A novel process model will help us get more from Moore

Moore's law, first formulated in 1965 by Gordon Moore and later revised to reflect even greater growth, says that the number of transistors on an integrated chip will double every two years. This exponential growth is behind almost every electronic technology we use today. The realisation that Moore's law is nearing its physical limit is spawning a new era of innovation. Three-dimensional (3D) integrated circuits are one of the best ways to get more from Moore's law. Hybrid bonding is quickly gaining ground as the preferred way to form high-density interconnects and 3D integration. The EU-funded H-3D-SOC project is developing the first-ever instruction set (design flow) for the processing of hybrid-bonded 3D systems-on-chip. It focusses on the embedded metal pads in the bond interface that enable face-to-face wafer connections and device stacking and could significantly advance the development of high-end processors.

Coordinator

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Net EU contribution
€ 178 320,00
Address
Kapeldreef 75
3001 Leuven
Belgium

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Region
Vlaams Gewest Prov. Vlaams-Brabant Arr. Leuven
Activity type
Research Organisations
Non-EU contribution
€ 0,00