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3D IC Design Flow for Hybrid-bonding 3D System on Chip

CORDIS provides links to public deliverables and publications of HORIZON projects.

Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .

Publications

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node (opens in new window)

Author(s): R Chen, G Sisto, A Jourdain, G Hiblot, M Stucchi, N Kakarla, B Chehab, SM Salahuddin, F Schleicher, A Veloso, G Hellings, P Weckx, D Milojevic, G Van der Plas, J Ryckaert, E Beyne
Published in: 2021 IEEE International Electron Devices Meeting (IEDM), Issue yearly, 2021, Page(s) 22.4. 1-22.4. 4
Publisher: IEEE
DOI: 10.1109/iedm19574.2021.9720528

IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and μ-& n-TSVs (opens in new window)

Author(s): G Sisto, B Chehab, B Genneret, R Baert, R Chen, P Weckx, J Ryckaert, R Chou, G van Der Plas, E Beyne, D Milojevic
Published in: 2021 IEEE International Interconnect Technology Conference (IITC), Issue yearly, 2020, Page(s) 1~3
Publisher: IEEE
DOI: 10.1109/iitc51362.2021.9537541

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited) (opens in new window)

Author(s): Giuliano Sisto; Rongmei Chen; Richard Chou; Geert Van der Plas; Eric Beyne; Rod Metcalfe; Dragomir Milojevic
Published in: 2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), Issue yearly, 2022
Publisher: IEEE
DOI: 10.1109/slip52707.2021.00011

3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes (opens in new window)

Author(s): R Chen, P Weckx, SM Salahuddin, S-W Kim, G Sisto, G Van der Plas, M Stucchi, R Baert, P Debacker, MH Na, J Ryckaert, D Milojevic, E Beyne
Published in: 2020 IEEE International Electron Devices Meeting (IEDM), Issue yearly, 2020, Page(s) 15.2. 1-15.2. 4
Publisher: IEEE
DOI: 10.1109/iedm13553.2020.9371905

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization (opens in new window)

Author(s): Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Issue montly, 2022, Page(s) 440-448, ISSN 1063-8210
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tvlsi.2022.3146064

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization (opens in new window)

Author(s): Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Issue montly, 2022, Page(s) 432-439, ISSN 1063-8210
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tvlsi.2022.3146125

Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node (opens in new window)

Author(s): Liu, Hsiao-Hsuan, Salahuddin, Shairfe M ; Abdi, Dawit ; Chen, Rongmei ; Weckx, Pieter ; Matagne, Philippe ; Catthoor, Francky
Published in: IEEE TRANSACTIONS ON ELECTRON DEVICES, Issue montly, 2022, Page(s) 3113 - 3117, ISSN 0018-9383
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2022.3165738

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