SECURE PLATFORM FOR ICT SYSTEMS ROOTED AT THE SILICON MANUFACTURING PROCESS

Livrables

The communication from both the WP5 RISCV processor and the WP2 HW RoT to the HLOS through the TEE is a significant step in SPIRS This deliverable demonstrates that communication a subset of the D31 specifications

TNED proof-of-concept

The TNED software architecture, its integration with OAM procedures, and the incorporation of an initial set of security functions will be demonstrated, using the initial implementations of the TEE and RoT. This deliverable will include an impact assessment for the different use cases, performed using the GDPR as the main guideline. This version of the TNED will be used for the initial use case demonstrations.

Website activation

SPIRS website will be the main promotional tool for communicating projects activities and results The website will also include a Restricted Area for the partners for easycommunicationdiscussion and exchange of information between the consortium members It will be

Report on the use cases and validation plan

The report will describe in detail the two use cases their possible vulnerabilities the security requirements and consolidates the specification of the custom SPIRS systems This first section of the report will be instrumental to provide useful feedback to WP3 and WP4 The second section of the report will describe in detail the validation plan

First VLSI integration of a lightweight RoT

The selection of the technology for VLSI integration will be described The selected hardware building blocks of RoT and simulation and available experimental results will be detailed

Publications

Protegiendo la identidad de las denuncias en un sistema abierto y auditable

Auteurs: S. Chica, A. Marín, D. Arroyo, J. Díaz
Publié dans: Proceedings Actas de la XVII Reunión Española sobre Criptología y Seguridad de la Información (RECSI 2022), 2022, Page(s) 68, ISBN 978-84-19024-14-5
Éditeur: Editorial de la Universidad de Cantabria

SoK: A Systematic Review of TEE Usage for Developing Trusted Applications

Auteurs: Arttu Paju; Muhammad Owais Javed; Juha Nurmi; Juha Savimäki; Brian McGillion; Billy Bob Brumley
Publié dans: The 18th International Conference on Availability, Reliability and Security (ARES 2023), Numéro 34, 2023, Page(s) 1-15, ISBN 9798400707728
Éditeur: Association for Computing Machinary, Inc.
DOI: 10.1145/3600160.3600169

About the Fujisaki-Okamoto Transformation in the Code-Based Algorithms of the NIST Post-quantum Call

Auteurs: Miguel Ángel González de la Torre, Luis Hernández Encinas
Publié dans: Proc. Conference 15th International Conference on Computational Intelligence in Security for Information Systems (CISIS 2022), Numéro Lecture Notes in Networks and Systems book series (LNNS,volume 532, 2022, Page(s) 75-85, ISBN 978-3-031-18409-3
Éditeur: Springer
DOI: 10.1007/978-3-031-18409-3_8

Secure Platform for ICT Systems Rooted at the Silicon Manufacturing Process (SPIRS)

Auteurs: P. Brox, M. C. Martínez-Rodríguez, D. Arroyo
Publié dans: Proceedings JNIC 2022 (VII Jornadas Nacionales de Investigación en Ciberseguridad 2022), 2022, Page(s) 363-366, ISBN 978-84-88734-13-6
Éditeur: Fundación Tecnalia Research and Innovation

True Random Number Generator based on RO-PUF

Auteurs: Luis F. Rojas Muñoz, Santiago Sánchez Solano, Macarena C. Martínez-Rodríguez, Piedad Brox
Publié dans: 37th Conference on Design of Circuits and Integrated Circuits (DCIS) 2022, Numéro 16-18 November 2022, 2022, ISBN 978-1-6654-5950-1
Éditeur: IEEE
DOI: 10.1109/dcis55711.2022.9970032

A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem

Auteurs: E. Camacho-Ruiz, S. Sánchez-Solano, M. C. Martínez-Rodríguez, E. Tena-Sánchez, P. Brox
Publié dans: 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS), 2023, ISSN 2640-5563
Éditeur: IEEE
DOI: 10.1109/dcis58620.2023.10336001

Design Flow to Evaluate the Performance of Ring Oscillator PUFs on FPGAs

Auteurs: Macarena C. Martínez-Rodríguez; Eros Camacho-Ruiz; Santiago Sánchez-Solano; Piedad Brox
Publié dans: 2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS), Numéro 24-26 Nov. 2021, 2021, ISBN 978-1-6654-2116-4
Éditeur: IEEE
DOI: 10.1109/dcis53048.2021.9666190

A complete SHA-3 hardware library based on a high efficiency Keccak design

Auteurs: E. Camacho, S. Sánchez-Solano, M. C. Martínez, P. Brox
Publié dans: 2023 IEEE Nordic Circuits and Systems Conference (NorCAS), 2023, Page(s) 1-7, ISBN 979-8-3503-3757-0
Éditeur: IEEE
DOI: 10.1109/norcas58970.2023.10305448

Diseño y evaluación de las prestaciones de funciones físicas no clonables basadas en osciladores en anillo sobre FPGAs

Auteurs: M. C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Brox, S. Sánchez-Solano
Publié dans: Proceedings JNIC 2022 (VII Jornadas Nacionales de Investigación en Ciberseguridad 2022), 2022, Page(s) 298-299, ISBN 978-84-88734-13-6
Éditeur: Fundación Tecnalia Research and Innovation

HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip

Auteurs: A. Karmakar, S. Sánchez-Solano, M. C. Martínez-Rodríguez, P. Brox
Publié dans: 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS), 2023, ISBN 979-8-3503-0385-8
Éditeur: IEEE
DOI: 10.1109/dcis58620.2023.10335970

A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks

Auteurs: V. Zúñiga, E. Tena, A. J. Acosta
Publié dans: 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS), 2023, ISBN 979-8-3503-0385-8
Éditeur: IEEE
DOI: 10.1109/dcis58620.2023.10336003

Review of Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA

Auteurs: F. E. Potestad-Ordoñez, E. Tena-Sánchez, C. Fernández-García, V. Zúñiga-González, J. M. Mora Gutiérrez, C. Baena-Oliva, P. Parra-Fernández, A. J. Acosta-Jiménez, C. J. Jiménez-Fernández
Publié dans: Proceedings JNIC 2022 (VII Jornadas Nacionales de Investigación en Ciberseguridad 2022), 2022, Page(s) 271-272, ISBN 978-84-88734-13-6
Éditeur: Fundación Tecnalia Research and Innovation

Hardware dedicado para la optimización temporal del algoritmo NTRU

Auteurs: E. Camacho-Ruiz, M. C. Martínez-Rodríguez, S. Sánchez-Solano, P. Brox
Publié dans: Proccedings JNIC 2022 (VII Jornadas Nacionales de Investigación en Ciberseguridad 2022), 2022, Page(s) 296-297, ISBN 978-84-88734-13-6
Éditeur: Fundación Tecnalia Research and Innovation

About the FrodoKEM lattice-based algorithm

Auteurs: M. A. González de la Torre, L. Hernández Encinas, A. Queiruga Dios
Publié dans: Proceedings JNIC 2022 (VII Jornadas Nacionales de Investigación en Ciberseguridad 2022), 2022, Page(s) 253-256, ISBN 978-84-88734-13-6
Éditeur: Fundación Tecnalia Research and Innovation

Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks

Auteurs: E. Tena-Sánchez, F. E. Potestad-Ordoñez, V. Zúñiga-González, C. Fernández-García, J. M. Mora Gutiérrez, C. J. Jiménez-Fernández, A. J. Acosta-Jiménez
Publié dans: Proceedings JNIC 2022 (VII Jornadas Nacionales de Investigación en Ciberseguridad 2022), 2022, Page(s) 290-291, ISBN 978-84-88734-13-6
Éditeur: Fundación Tecnalia Research and Innovation

Malware Finances and Operations: a Data-Driven Study of the Value Chain for Infections and Compromised Access

Auteurs: Juha Nurmi; Mikko Niemelä; Billy Bob Brumley
Publié dans: ARES '23: Proceedings of the 18th International Conference on Availability, Reliability and Security, Numéro 108, 2023, Page(s) 1-12, ISBN 9798400707728
Éditeur: Association for Computing Machinery
DOI: 10.1145/3600160.3605047

Comparative analysis of lattice-based post-quantum cryptosystems

Auteurs: M. A. González de la Torre, J. I. Sánchez garcía, L. Hernández Encinas
Publié dans: Proceedings Actas de la XVII Reunión Española sobre Criptología y Seguridad de la Información (RECSI 2022), 2022, Page(s) 121, ISBN 978-84-19024-14-5
Éditeur: Editorial de la Universidad de Cantabria
DOI: 10.22429/euc2022.028

Enhancing the anonymity and auditability of whistleblowers protection

Auteurs: S. Chica, A. Marín, D. Arroyo, J. Díaz, F. Almenares, and D. Díaz
Publié dans: Workshop on Beyond the promises of web3.0: foundations and challenges of trust decentralization (WEB3-TRUST), 2022
Éditeur: Springer
DOI: 10.20350/digitalcsic/14702

On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices

Auteurs: L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Publié dans: Sensors, Numéro vol. 23, no. 8, article 4070, 2023, ISSN 1424-8220
Éditeur: Multidisciplinary Digital Publishing Institute (MDPI)
DOI: 10.3390/s23084070

Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher

Auteurs: F. E. Potestad-Ordóñez, E. Tena-Sánchez, A. J. Acosta-Jiménez, C. J. Jiménez-Fernández, R. Chaves
Publié dans: IEEE Access, Numéro Volume 10, 2022, Page(s) 65548 - 65561, ISSN 2169-3536
Éditeur: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2022.3183764

Multi-Unit Serial Polynomial Multiplier to Accelerate NTRU-Based Cryptographic Schemes in IoT Embedded Systems

Auteurs: Santiago Sánchez-Solano, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez and Piedad Brox
Publié dans: Sensors, Numéro 22 (5), 2057, 2022, ISSN 1424-8220
Éditeur: Multidisciplinary Digital Publishing Institute (MDPI)
DOI: 10.3390/s22052057

Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs

Auteurs: Ignacio M. Delgado-Lozano; Erica Tena-Sánchez; Juan Núñez; Antonio J. Acosta
Publié dans: IEEE Embedded Systems Letters, Numéro Early Access, 2021, ISSN 1943-0663
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/les.2021.3122395

Timing-Attack-Resistant Acceleration of NTRU Round 3 Encryption on Resource-Constrained Embedded Systems

Auteurs: E. Camacho-Ruiz, M.C. Martínez-Rodríguez, S. Sánchez-Solano and P. Brox
Publié dans: Cryptography, Numéro vol. 7, no.2, article 29, 2023, ISSN 2410-387X
Éditeur: Multidisciplinary Digital Publishing Institute
DOI: 10.3390/cryptography7020029

Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks

Auteurs: Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Carlos J. Jiménez-Fernández, Antonio J. Acosta, Ricardo Chaves
Publié dans: Applied Sciences, Numéro 12 (5), 2390, 2022, ISSN 2076-3417
Éditeur: MDPI
DOI: 10.3390/app12052390

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations

Auteurs: Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sanchez; J. M. Mora-Gutiérrez; Manuel Valencia-Barrero; C. J. Jimenez-Fernandez
Publié dans: Sensors (Basel, Switzerland), Numéro 21(22), 7596, 2021, ISSN 1424-8220
Éditeur: Multidisciplinary Digital Publishing Institute (MDPI)
DOI: 10.3390/s21227596

Analysis of the FO Transformation in the Lattice-Based Post-Quantum Algorithms

Auteurs: M.A. González de la Torre, L. Hernández Encinas, and A. Queiruga-Dios
Publié dans: Mathematics, Numéro 10 (16), 2967, 2022, ISSN 2227-7390
Éditeur: MDPI
DOI: 10.3390/math10162967

Efficient RO-PUF for Generation of Identifiers and Keys in Resource-Constrained Embedded Systems

Auteurs: Macarena C. Martínez-Rodríguez, Luis F. Rojas-Muñoz, Eros Camacho-Ruiz, Santiago Sánchez-Solano and Piedad Brox
Publié dans: Cryptography, Numéro 2410387X, 2022, Page(s) 51, ISSN 2410-387X
Éditeur: MPDI
DOI: 10.3390/cryptography6040051

Hardware Countermeasures Benchmarking against Fault Attacks

Auteurs: Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Antonio José Acosta-Jiménez, Carlos Jesús Jiménez-Fernández and Ricardo Chaves
Publié dans: Applied Sciences, Numéro 12 (5), 2443, 2022, ISSN 2076-3417
Éditeur: MDPI
DOI: 10.3390/app12052443

True Random Number Generation Capability of a Ring Oscillator PUF for Reconfigurable Devices

Auteurs: L. Felipe Rojas-Muñoz, Santiago Sánchez-Solano, Macarena. C. Martínez-Rodríguez, Piedad Brox
Publié dans: Electronics, Numéro 11(23), 4028, 2022, Page(s) 1-24, ISSN 2079-9292
Éditeur: MPDI
DOI: 10.3390/electronics11234028

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