Objective
The project aims to produce a high level synthesis tool for automatic design of interface circuits.
Timing diagrams, used to express interactions between the systems to be interfaced, will be annotated with quantitative timing constraints and with VHDL expressions to specify operations on data. This specification will be automatically transformed into an FPGA based implementration in several steps:
- transformation of timing diagrams into a set of cooperating FSMs (data & control)
- consideration of pipelining to get high performance circuits
- introduction of asynchronous sub-circuits to fulfill hard timing constraints
- partitioning and re-partitioning techniques for FSMs
- timing driven technology mapping and layout for controller and data path.
European links:
Results of the ESPRIT project 6128 FORMAT are used in this project.
INFORMATION DISSEMINATION ACTIVITIES AND EXPLOITATION
The project partners will establish contacts with tool vendors for possible commercialisation of the tool.
Fields of science (EuroSciVoc)
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Programme(s)
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Multi-annual funding programmes that define the EU’s priorities for research and innovation.
Topic(s)
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Calls for proposals are divided into topics. A topic defines a specific subject or area for which applicants can submit proposals. The description of a topic comprises its specific scope and the expected impact of the funded project.
Call for proposal
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Funding Scheme
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Funding scheme (or “Type of Action”) inside a programme with common features. It specifies: the scope of what is funded; the reimbursement rate; specific evaluation criteria to qualify for funding; and the use of simplified forms of costs like lump sums.
Coordinator
94032 Passau
Germany
The total costs incurred by this organisation to participate in the project, including direct and indirect costs. This amount is a subset of the overall project budget.