Objectif
The project aims to produce a high level synthesis tool for automatic design of interface circuits.
Timing diagrams, used to express interactions between the systems to be interfaced, will be annotated with quantitative timing constraints and with VHDL expressions to specify operations on data. This specification will be automatically transformed into an FPGA based implementration in several steps:
- transformation of timing diagrams into a set of cooperating FSMs (data & control)
- consideration of pipelining to get high performance circuits
- introduction of asynchronous sub-circuits to fulfill hard timing constraints
- partitioning and re-partitioning techniques for FSMs
- timing driven technology mapping and layout for controller and data path.
European links:
Results of the ESPRIT project 6128 FORMAT are used in this project.
INFORMATION DISSEMINATION ACTIVITIES AND EXPLOITATION
The project partners will establish contacts with tool vendors for possible commercialisation of the tool.
Thème(s)
Data not availableAppel à propositions
Data not availableRégime de financement
CSC - Cost-sharing contractsCoordinateur
94032 Passau
Allemagne