Low mechanical stress and low, uniform electrical resistivity are of crucial importance for metallisation of IC devices with feature sizes of deep submicron (below 0.5 um) dimensions. Two major research areas of interest are investigated in order to enhance circuit performance and to improve yield:
SALICIDE TiSi2 is employed for local metallisation of IC devices. The formation, morphology and thermal stability of TiSi2 will be studied on patterned structures of deep submicron dimensions. Simple modifications to the fabrication process are implemented to improve the silicide formation and thermal stability.
The W plug technology with a W/TiN/Ti stack is utilised to realise multilayer-multilevel metallisation. CVD-W is deposited on
sputter-deposited TiN/Ti adhesion layers. Different process techniques (post-annealing of TiN/Ti, modification of W deposition) are investigated, in order to control the high mechanical stresses and impurity levels in the W layers.