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Contenido archivado el 2024-05-24

Ballistic Double Electron Waveguide for Potential Use in Analog-to-digital conversion.


This proposal aims at realizing a new electron device which can be potentially used for very high-speed (GS/s), low-power (about 1 µW), high-resolution (at least 5 bits), analog-to-digital conversion to answer the demand in industrial sectors of telecommunications and radar systems. The concept of this device, named DEW, derives from the well-known staircase conductance of ballistic electron wave guides. The device concept predicts an output conductance that should be a periodic square wave. This is the second phase of a two-phase project. During the first phase, the device concept of DEW was experimentally established at low temperatures (up to 4.2 K) using devices fabricated from AlGaAs/GaAs heterostrucutres. The objective of the second phase is to deliver DEW devices fabricated from antimonide semiconductor quantum-well structures and capable of operation at temperatures up to 77K. Structures such as InAlSb/InSb, AlGaSb/InAs, and AlSb/InAsSb will be designed, grown, and used for this purpose.

The tasks of this project will be carried out through a number of integrated thrusts, some running concurrently:
1. Design and Growth of Optimal Structures:- GaSb/InAs, AlSb/InAs, AlGaSb/InAs and InAlSb/InSb QW structures will be designed, grown, and characterized to yield optimal electrical characteristics;
2. Optimizing Device Design and Device Fabrication:- The DEW design of the first phase will be optimised and used to fabricate DEWs from AlGaAs/GaAs heterostructures. Such devices are named GDEWs; - A study of ohmic and Schottky gate metallization on antimonide QW structures cited above will be undertaken; - The above antimonide QW structures will be used to fabricate DEWs. Such DEWs are called ADEWs.
3. Device Characterization: - Output conductance DG will be measured at low frequency (up to 1kHz) and at temperatures up to 77 K to check a square-wave DG and the maximum temperature at which this is retained; - The intrinsic gate capacitance and RC time constant of DEWs will be extracted through the use of an equivalent circuit that will be developed; - High-speed characterization of DEWs will be carried out to establish operational device characteristics. All the optimisation processes described above will be carried out in an iterative way with all the partners involved. The consortium will meet periodically along with the industrial advisors to review progress against the key objectives and to plan future steps.

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Convocatoria de propuestas

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Régimen de financiación

CSC - Cost-sharing contracts


Aportación de la UE
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75752 PARIS CEDEX 15

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Participantes (3)