Wave-Locked Loop for Frequency Synthesis (WLL)

Publications

Conference proceedings (2)

A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f 3 corner

Author(s): Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
Published in: ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, Page(s) 87-90
DOI: 10.1109/esscirc.2017.8094532

A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS

Author(s): Peng Chen, Feifei Zhang, Zhirui Zong, Hao Zheng, Teerachot Siriburanon, Robert Bogdan Staszewski
Published in: 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2017, Page(s) 93-96
DOI: 10.1109/asscc.2017.8240224

Peer reviewed articles (2)

Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators

Author(s): Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, Page(s) 1-1, ISSN 1549-7747
DOI: 10.1109/tcsii.2019.2896483

A Low-Flicker-Noise 30-GHz Class-F 23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path

Author(s): Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
Published in: IEEE Journal of Solid-State Circuits, Issue 53/7, 2018, Page(s) 1977-1987, ISSN 0018-9200
DOI: 10.1109/jssc.2018.2818681