Integrated Modelling, Fault Management, Verification and Reliable Design Environment for Cyber-Physical Systems

Autores: Thiago Copetti, Guilherme Medeiros, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar
Publicado en: 2016 17th Latin-American Test Symposium (LATS), 2016, Página(s) 75-80, ISBN 978-1-5090-1331-9
Editor: IEEE
DOI: 10.1109/LATW.2016.7483343

A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage

Autores: Anton Karputkin, Jaan Raik
Publicado en: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, Página(s) 1124-1127, ISBN 978-3-9815370-7-9
Editor: Research Publishing Services
DOI: 10.3850/9783981537079_0260

Counterexample-guided diagnosis

Autores: Heinz Riener, Goerschwin Fey
Publicado en: 2016 1st IEEE International Verification and Security Workshop (IVSW), 2016, Página(s) 1-6, ISBN 978-1-5090-1141-4
Editor: IEEE
DOI: 10.1109/IVSW.2016.7566605

Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems

Autores: Hans G. Kerkhoff, Ghazanfar Ali, Jinbo Wan, Ahmed Ibrahim, Jerrin Pathrose
Publicado en: 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2017, Página(s) 1-6, ISBN 978-1-5386-2880-5
Editor: IEEE
DOI: 10.1109/VLSI-SoC.2017.8203464

An automotive MP-SoC featuring an advanced embedded instrument infrastructure for high dependability

Autores: Hans G. Kerkhoff, Ghazanfar Ali, Hassan Ebrahimi, Ahmed Ibrahim
Publicado en: 2017 International Test Conference in Asia (ITC-Asia), 2017, Página(s) 65-70, ISBN 978-1-5386-3051-8
Editor: IEEE
DOI: 10.1109/ITC-ASIA.2017.8097113

A dependable AMR sensor system for automotive applications

Autores: Andreina Zambrano, Hans G. Kerkhoff
Publicado en: 2017 International Test Conference in Asia (ITC-Asia), 2017, Página(s) 59-64, ISBN 978-1-5386-3051-8
Editor: IEEE
DOI: 10.1109/ITC-ASIA.2017.8097112

Structured scan patterns retargeting for dynamic instruments access

Autores: Ahmed Ibrahim, Hans G. Kerkhoff
Publicado en: 2017 IEEE 35th VLSI Test Symposium (VTS), 2017, Página(s) 1-6, ISBN 978-1-5090-4482-5
Editor: IEEE
DOI: 10.1109/VTS.2017.7928955

A cost-efficient dependability management framework for self-aware system-on-chips based on IEEE 1687

Autores: Ahmed Ibrahim, Hans G. Kerkhoff
Publicado en: 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, Página(s) 1-2, ISBN 978-1-5386-0352-9
Editor: IEEE
DOI: 10.1109/IOLTS.2017.8046166

Multi-fragment Markov model guided online test generation for MPSoC

Autores: Vain, Jüri; Tsiopoulos, Leonidas; Kharchenko, Vyacheslav; Kaur, Apneet; Jenihhin, Maksim; Raik, Jaan
Publicado en: 2017
Editor: ICT in Education, Research and Industrial Applications

High-level test generation for processing elements in many-core systems

Autores: Adeboye Stephen Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik
Publicado en: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Página(s) 1-8, ISBN 978-1-5386-3344-1
Editor: IEEE
DOI: 10.1109/ReCoSoC.2017.8016156

Fault-resilient NoC router with transparent resource allocation

Autores: Tsotne Putkaradze, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan
Publicado en: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Página(s) 1-8, ISBN 978-1-5386-3344-1
Editor: IEEE
DOI: 10.1109/ReCoSoC.2017.8016161

Run-time reconfigurable instruments for advanced board-level testing

Autores: Igor Aleksejev, Artur Jutman, Sergei Devadze
Publicado en: 2016 IEEE AUTOTESTCON, 2016, Página(s) 1-8, ISBN 978-1-5090-0790-5
Editor: IEEE
DOI: 10.1109/AUTEST.2016.7589627

Embedded instrumentation toolbox for screening marginal defects and outliers for production

Autores: Sergei Odintsov, Artur Jutman, Sergei Devadze, Igor Aleksejev
Publicado en: 2017 IEEE AUTOTESTCON, 2017, Página(s) 1-9, ISBN 978-1-5090-4922-6
Editor: IEEE
DOI: 10.1109/AUTEST.2017.8080516

Marginal PCB assembly defect detection on DDR3/4 memory bus

Autores: Sergei Odintsov, Artur Jutman, Sergei Devadze
Publicado en: 2017 IEEE International Test Conference (ITC), 2017, Página(s) 1-10, ISBN 978-1-5386-3413-4
Editor: IEEE
DOI: 10.1109/TEST.2017.8242070

Synthesis of Admissible Shield

Autores: Laura Humphrey, Bettina Könighofer, Robert Könighofer, Ufuk Topcu
Publicado en: 2017, Página(s) 134-151
Editor: Springer International Publishing
DOI: 10.1007/978-3-319-49052-6_9

Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects

Autores: Tino Flenker, Jan Malburg, Gorschwin Fey, Serhiy Avramenko, Massimo Violante, Matteo Sonza Reorda
Publicado en: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Página(s) 533-538, ISBN 978-1-5090-6762-6
Editor: IEEE
DOI: 10.1109/ISVLSI.2017.99

Formal Verification of Masked Hardware Implementations in the Presence of Glitches

Autores: Roderick Bloem, Hannes Gross, Rinat Iusupov, Bettina Konighofer, Stefan Mangard, and Johannes Winter
Publicado en: 2018
Editor: EUROCRYPT

Intermittent Resistance Fault Detection at Board Level

Autores: H. Ebrahimi and H.G. Kerkhoff
Publicado en: 2018
Editor: DDECS

On-Chip Lifetime Prediction for Dependable Many-Processor SoCs based on Slack-Delay and IDDX Data Fusion

Autores: G. Ali, J. Pathrose, Y. Zhao and H.G. Kerkhoff
Publicado en: 2018
Editor: submitted to International Test Conference Asia (ITC-Asia)

IJTAG Compatible Analogue Embedded Instruments for MPSoC Life-time Prediction

Autores: J.Pathrose, G.Ali, and H. G. Kerkhoff
Publicado en: 2018
Editor: 2018 19th IEEE Latin American Test Symposium (LATS)

Mining Latency Guarantees for RTL Designs

Autores: Malburg, Jan and Riener, Heinz and Fey, Görschwin
Publicado en: 2018
Editor: IEEE International Symposium on Multiple-Valued Logic

SMT-Based CPS Parameter Synthesis

Autores: Heinz Riener, Robert Könighofer, Görschwin Fey, and Roderick Bloem (DLR, TU Graz)
Publicado en: Applied Verification for Continuous and Hybrid Systems, 2016
Editor: ARCH'16

Synchronization, Calibration and Triggering of IEEE 1687 Embedded Instruments

Autores: A. Jutman, S. Devadze, K. Shibin (Testonica Lab)
Publicado en: 2016, Página(s) 1-6
Editor: WRTLT’2016

Accessing on-chip temperature health monitors using the IEEE 1687 standard

Autores: Ali, G. and Badawy, A. and Kerkhoff, H.G. (U.Twente)
Publicado en: 2016, Página(s) 776-779
Editor: IEEE Circuits & Systems Society

A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing

Autores: Zhao, Yong and Kerkhoff, H.G. (U.Twente)
Publicado en: 2016, Página(s) 10-14
Editor: IEEE Computer Society

Gate-Level Modelling of NBTI-Induced Delays Under Process Variations

Autores: Copetti, Thiago; Medeiros, Guilherme; Poehls, Leticia; Vargas, Fabian; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan (Tallinn UT)
Publicado en: 2016, Página(s) 75-80
Editor: IEEE Computer Society Press

Counterexample-Guided Diagnosis

Autores: Heinz Riener and Goerschwin Fey (DLR)
Publicado en: 2016
Editor: IVSW

Synthesizing adaptive test strategies from temporal logic specifications

Autores: Roderick Bloem, Robert Konighofer, Ingo Pill, Franz Rock
Publicado en: 2016 Formal Methods in Computer-Aided Design (FMCAD), 2016, Página(s) 17-24, ISBN 978-0-9835678-6-8
Editor: IEEE
DOI: 10.1109/FMCAD.2016.7886656

SoCDep²: A framework for dependable task deployment on many-core systems under mixed-criticality constraints

Autores: Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT)
Publicado en: 2016
Editor: ReCoSoC

Logic-based implementation of fault-tolerant routing in 3D network-on-chips

Autores: Behrad Niazmand, Siavoosh Payandeh Azad, Jose Flich, Jaan Raik, Gert Jervan, Thomas Hollstein
Publicado en: 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2016, Página(s) 1-8, ISBN 978-1-4673-9030-9
Editor: IEEE
DOI: 10.1109/NOCS.2016.7579317

Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems

Autores: Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT)
Publicado en: 2016
Editor: DREAMCloud

Online digital compensation Method for AMR sensors

Autores: Andreina Zambrano, Hans G. Kerkhoff
Publicado en: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, Página(s) 1-6, ISBN 978-1-5090-3561-8
Editor: IEEE
DOI: 10.1109/VLSI-SoC.2016.7753579

Determination of the drift of the maximum angle error in AMR sensors due to aging

Autores: Andreina Zambrano, Hans G. Kerkhoff
Publicado en: 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW), 2016, Página(s) 1-5, ISBN 978-1-5090-2751-4
Editor: IEEE
DOI: 10.1109/IMS3TW.2016.7524234

WCET overapproximation for software in the context of a Cyber-Physical System

Autores: Niklas Krafczyk, Heinz Riener, Goerschwin Fey
Publicado en: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, Página(s) 1-6, ISBN 978-1-5090-3561-8
Editor: IEEE
DOI: 10.1109/VLSI-SoC.2016.7753559

Exact diagnosis using boolean satisfiability

Autores: Heinz Riener, Goerschwin Fey
Publicado en: Proceedings of the 35th International Conference on Computer-Aided Design - ICCAD '16, 2016, Página(s) 1-8, ISBN 9781-450344661
Editor: ACM Press
DOI: 10.1145/2966986.2967036

Multilevel design understanding - from specification to logic invited paper

Autores: Sandip Ray, Ian G. Harris, Goerschwin Fey, Mathias Soeken
Publicado en: Proceedings of the 35th International Conference on Computer-Aided Design - ICCAD '16, 2016, Página(s) 1-6, ISBN 9781-450344661
Editor: ACM Press
DOI: 10.1145/2966986.2980093

Towards an automated and reusable in-field self-test solution for MPSoCs

Autores: Ahmed Ibrahim, Hans G. Kerkhoff
Publicado en: 2016 28th International Conference on Microelectronics (ICM), 2016, Página(s) 249-252, ISBN 978-1-5090-5721-4
Editor: IEEE
DOI: 10.1109/ICM.2016.7847862

Efficient utilization of hierarchical iJTAG networks for interrupts management

Autores: Ahmed Ibrahim, Hans G. Kerkhoff
Publicado en: 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016, Página(s) 97-102, ISBN 978-1-5090-3623-3
Editor: IEEE
DOI: 10.1109/DFT.2016.7684077

Analysis and design of an on-chip retargeting engine for IEEE 1687 networks

Autores: Ahmed Ibrahim, Hans G. Kerkhoff
Publicado en: 2016 21th IEEE European Test Symposium (ETS), 2016, Página(s) 1-6, ISBN 978-1-4673-9659-2
Editor: IEEE
DOI: 10.1109/ETS.2016.7519301

Thermal issues in test: An overview of the significant aspects and industrial practice

Autores: J. Alt, P. Bernardi, A. Bosio, R. Cantoro, H. Kerkhoff, A. Leininger, W. Molzer, A. Motta, C. Pacha, A. Pagani, A. Rohani, R. Strasser
Publicado en: 2016 IEEE 34th VLSI Test Symposium (VTS), 2016, Página(s) 1-4, ISBN 978-1-4673-8454-4
Editor: IEEE
DOI: 10.1109/VTS.2016.7477278

Designing reliable cyber-physical systems overview associated to the special session at FDL'16

Autores: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Konighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Rock, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Publicado en: 2016 Forum on Specification and Design Languages (FDL), 2016, Página(s) 1-8, ISBN 979-10-92279-17-7
Editor: IEEE
DOI: 10.1109/FDL.2016.7880382

Mining Latency Guarantees for RT-level Designs

Autores: Jan Malburg, Heinz Riener, Goerschwin Fey (DLR)
Publicado en: 2017
Editor: DUHDe

Computing Exact Fault Candidates Incrementally

Autores: Heinz Riener and Goerschwin Fey (DLR)
Publicado en: 2017
Editor: DUHDe

Mapping Abstract and Concrete Hardware Models for Design Understanding

Autores: Tino Flenker and Goerschwin Fey (DLR)
Publicado en: 2017
Editor: DDECS

Counterexample-Guided EF Synthesis of Boolean Functions

Autores: Heinz Riener, Ruediger Ehlers, and Goerschwin Fey (DLR)
Publicado en: 2017
Editor: MBMV

Comprehensive Performance and Robustness Analysis of 2D Turn Models for Network-on-Chips

Autores: Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT)
Publicado en: 2017
Editor: ISCAS

Automated Area and Coverage Optimization of Minimal Latency Checkers

Autores: Siavoosh Payandeh Azad, Behrad Niazmand, Apneet Kaur Sandhu, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT)
Publicado en: 2017
Editor: IEEE

From Online Fault Detection to Fault Management in NoC Routers: A Ground-up Approach

Autores: Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Adeboye Stephen Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein (Tallinn UT)
Publicado en: 2017
Editor: DDECS

CEGAR-based EF Synthesis of Boolean Functions with an Application to Circuit Rectification

Autores: Heinz Riener, Rüdiger Ehlers, Görschwin Fey (DLR)
Publicado en: 2017
Editor: ASP-DAC’17

Property Mining using Dynamic Dependency Graphs

Autores: Jan Malburg, Tino Flenker, Görschwin Fey (DLR)
Publicado en: 2017
Editor: ASP-DAC
DOI: 10.1109/ASPDAC.2017.7858327

Synthesizing cooperative reactive mission plans

Autores: Rudiger Ehlers, Robert Konighofer, Roderick Bloem
Publicado en: 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), 2015, Página(s) 3478-3485, ISBN 978-1-4799-9994-1
Editor: IEEE
DOI: 10.1109/IROS.2015.7353862

Immortalizing many-core systems early experiences of the horizon 2020 action IMMORTAL

Autores: Jaan Raik
Publicado en: 2015 International Conference on High Performance Computing & Simulation (HPCS), 2015, Página(s) 561-562, ISBN 978-1-4673-7813-0
Editor: IEEE
DOI: 10.1109/HPCSim.2015.7237092

On-line Fault Classification and Handling in IEEE1687 based Fault Management System for Complex SoCs

Autores: K. Shibin, S. Devadze, A. Jutman
Publicado en: 2016
Editor: IEEE

A hybrid algorithm to conservatively check the robustness of circuits

Autores: Niels Thole, Lorena Anghel, and Goerschwin Fey
Publicado en: 2016
Editor: IEEE

SMT-Based CPS Parameter Synthesis

Autores: Heinz Riener, Robert Könighofer, Görschwin Fey, and Roderick Bloem
Publicado en: 2016
Editor: IEEE

On-line Monitoring of Maximum Angle Error in AMR Sensors

Autores: A. Zambrano
Publicado en: 2016
Editor: IOLTS

Matching abstract and concrete hardware models for design understanding

Autores: Tino Flenker and Goerschwin Fey
Publicado en: 2016
Editor: IEEE

Online Management of Temperature Health Monitors using the IEEE 1687 Standard

Autores: G. Ali , A. Badewy and H.G. Kerkhoff
Publicado en: 2016
Editor: IEEE

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Autores: Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan, Gert Jervan, Thomas Hollstein
Publicado en: 2015 Euromicro Conference on Digital System Design, 2015, Página(s) 288-292, ISBN 978-1-4673-8035-5
Editor: IEEE
DOI: 10.1109/DSD.2015.15

Automated minimization of concurrent online checkers for Network-on-Chips

Autores: Pietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan, Thomas Hollstein
Publicado en: 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, Página(s) 1-8, ISBN 978-1-4673-7942-7
Editor: IEEE
DOI: 10.1109/ReCoSoC.2015.7238079

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers

Autores: Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Vineeth Govind, Thomas Hollstein, Gert Jervan, Ranganathan Hariharan
Publicado en: Proceedings of the 9th International Symposium on Networks-on-Chip - NOCS '15, 2015, Página(s) 1-8, ISBN 9781-450333962
Editor: ACM Press
DOI: 10.1145/2786572.2788713

A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage

Autores: Karputkin, Anton; Raik, Jaan
Publicado en: 2016
Editor: IEEE

New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams

Autores: Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar
Publicado en: 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015, Página(s) 251-254, ISBN 978-1-4799-6780-3
Editor: IEEE
DOI: 10.1109/DDECS.2015.56

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

Autores: Jenihhin, Maksim; Squillero, Giovanni; Copetti, Thiago Santos; Tihhomirov, Valentin; Kostin, Sergei; Gaudesi, Marco; Vargas, Fabian; Raik, Jaan; Sonza Reorda, Matteo; Bolzani Poehls, Leticia; Ubar, Raimund; Medeiros, Guilherme Cardoso
Publicado en: Journal of Electronic Testing-Theory and Applications (JETTA), 2016
Editor: SPRINGER

Semi-Formal Methods for Soft Error Analysis

Autores: Patrick Klampfl, Robert Könighofer, Roderick Bloem, Ayrat Khalimov, Aiman Abu-Yonis, Shiri Moran
Publicado en: 2017
Editor: CoRR abs/1712.04291

Designing Reliable Cyber-Physical Systems, Lecture Notes in Electrical Engineering: Languages, Design Methods, and Tools for Electronic System Design

Autores: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Shlomit Koyfman, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Publicado en: 2018, Página(s) 15-38
Editor: Springer International Publishing
DOI: 10.1007/978-3-319-62920-9_2

Design and Implementation of a dependable CPSoC for Automotive Applications

Autores: G. Ali, H. Ebrahimi, J. Pathrose and H.G. Kerkhoff
Publicado en: 2018
Editor: submitted to Industrial Cyber-Physical Systems (ICPS)

A Flexible Distributed Simulation Environment for Cyber-Physical Systems Using ZeroMQ

Autores: Ofenloch, Annika and Greif, Fabian
Publicado en: Journal of Communications, 2018
Editor: Journal of Communications

Reliable Health Monitoring and Fault Management Infrastructure based on Embedded Instrumentation and IEEE 1687

Autores: A. Jutman, K. Shibin, S. Devadze (Testonica Lab)
Publicado en: 2016, Página(s) 240-249
Editor: AUTOTESTCON’2016

Learning Models of a Network Protocol using Neural Network Language Models

Autores: Bernhard Aichernig, Roderick Bloem, Franz Pernkopf, Franz Röck, Tobias Schrank and Martin Tappler (TU Graz)
Publicado en: 2016
Editor: IEEE Symposium on Security and Privacy

Killing strategies for model-based mutation testing

Autores: Bernhard K. Aichernig, Harald Brandl, Elisabeth Jöbstl, Willibald Krenn, Rupert Schlick, Stefan Tiran
Publicado en: Software Testing, Verification and Reliability, Edición 25/8, 2015, Página(s) 716-748, ISSN 0960-0833
Editor: John Wiley & Sons Inc.
DOI: 10.1002/stvr.1522

Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure

Autores: Konstantin Shibin, Sergei Devadze, Artur Jutman, Martin Grabmann, Robin Pricken
Publicado en: IEEE Design & Test, Edición 34/6, 2017, Página(s) 27-35, ISSN 2168-2356
Editor: IEEE Computer Society
DOI: 10.1109/MDAT.2017.2750902

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

Autores: Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
Publicado en: Journal of Electronic Testing, Edición 32/3, 2016, Página(s) 273-289, ISSN 0923-8174
Editor: Kluwer Academic Publishers
DOI: 10.1007/s10836-016-5589-x

metaSMT: focus on your application and not on solver integration

Autores: Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Goerschwin Fey
Publicado en: International Journal on Software Tools for Technology Transfer, 2016, ISSN 1433-2779
Editor: Springer Verlag
DOI: 10.1007/s10009-016-0426-1

Debugging hardware designs using dynamic dependency graphs

Autores: Jan Malburg, Alexander Finder, Görschwin Fey (DLR)
Publicado en: Journal of Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), 2016, ISSN 0141-9331
Editor: Elsevier BV

Simulating NBTI Degradation in Arbitrary Stressed Analog/Mixed-Signal Environments

Autores: Jinbo Wan, Hans Kerkhoff, Jaap Bisschop
Publicado en: IEEE Transactions on Nanotechnology, 2016, Página(s) 1-1, ISSN 1536-125X
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TNANO.2015.2505092

Energy Efficient Multi-Fragment Markov Model Guided Online Model-Based Testing for MPSoC

Autores: Vain,Jüri; Tsiopoulos, Leonidas; Kharchenko, Vyacheslav; Kaur, Apneet; Jenihhin, Maksim; Raik, Jaan; Nõmm Sven
Publicado en: Green-IT Engineering: Social, Business and Industrial Applications (1−21), 2018
Editor: Springer

Cooperative Reactive Synthesis

Autores: Roderick Bloem, Rüdiger Ehlers, Robert Könighofer
Publicado en: Automated Technology for Verification and Analysis, 2015, Página(s) 394-410, ISBN 978-3-319-24953-7
Editor: Springer International Publishing
DOI: 10.1007/978-3-319-24953-7_29

Case Study: Automatic Test Case Generation for a Secure Cache Implementation

Autores: Roderick Bloem, Daniel Hein, Franz Röck, Richard Schumi
Publicado en: Tests and Proofs, 2015, Página(s) 58-75, ISBN 978-3-319-21215-9
Editor: Springer International Publishing
DOI: 10.1007/978-3-319-21215-9_4

Derechos de propiedad intelectual

ASSURING CHIP RELIABILITY WITH AUTOMATIC GENERATION OF DRIVERS AND ASSERTIONS

Número de solicitud/publicación: US 9483591
Fecha: 2015-11-27

ASSURING CHIP RELIABILITY WITH AUTOMATIC GENERATION OF DRIVERS AND ASSERTIONS

Número de solicitud/publicación: US 9483591
Fecha: 2015-11-27

Buscando datos de OpenAIRE...

Resultado final

Publicaciones

Derechos de propiedad intelectual

Compartir esta página

Descargar