Livrables Documents, reports (17) Online fault detection mechanisms Report Integrated demonstrator on modelling, verification and reliability analysis Report System-level reliability analysis tools Report FDIR schemes (incl. reconfiguration, health map, fault classification) Report Dynamic, semi-formal and formal reliability analysis tools report Fault management infrastructure verification tools Report Market analysis Report Status on fault management Report Verification, debugging and testing tools Report Dissemination and communication report Report Status on modelling, fault/reconfiguration modelling and reliability metrics Cross-layer CPS modelling framework Report Reconfiguration modelling Report CPS run-time for SW task deployment Report Dynamic, semi-formal and formal reliability analysis methods Report Fault models and reliability metrics Report Verification, debugging and testing methods Report Demonstrators, pilots, prototypes (2) Silicon demonstrator for fault management and mixed-signal reliability verification Demonstrator Integrated FPGA demonstrator of the fault management framework Demonstrator Websites, patent fillings, videos etc. (1) IMMORTAL Website and factsheet Website Publications Conference proceedings (63) Gate-level modelling of NBTI-induced delays under process variations Auteurs: Thiago Copetti, Guilherme Medeiros, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar Publié dans: 2016 17th Latin-American Test Symposium (LATS), 2016, Page(s) 75-80, ISBN 978-1-5090-1331-9 Éditeur: IEEE DOI: 10.1109/LATW.2016.7483343 A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage Auteurs: Anton Karputkin, Jaan Raik Publié dans: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, Page(s) 1124-1127, ISBN 978-3-9815370-7-9 Éditeur: Research Publishing Services DOI: 10.3850/9783981537079_0260 Counterexample-guided diagnosis Auteurs: Heinz Riener, Goerschwin Fey Publié dans: 2016 1st IEEE International Verification and Security Workshop (IVSW), 2016, Page(s) 1-6, ISBN 978-1-5090-1141-4 Éditeur: IEEE DOI: 10.1109/IVSW.2016.7566605 Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems Auteurs: Hans G. Kerkhoff, Ghazanfar Ali, Jinbo Wan, Ahmed Ibrahim, Jerrin Pathrose Publié dans: 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2017, Page(s) 1-6, ISBN 978-1-5386-2880-5 Éditeur: IEEE DOI: 10.1109/VLSI-SoC.2017.8203464 An automotive MP-SoC featuring an advanced embedded instrument infrastructure for high dependability Auteurs: Hans G. Kerkhoff, Ghazanfar Ali, Hassan Ebrahimi, Ahmed Ibrahim Publié dans: 2017 International Test Conference in Asia (ITC-Asia), 2017, Page(s) 65-70, ISBN 978-1-5386-3051-8 Éditeur: IEEE DOI: 10.1109/ITC-ASIA.2017.8097113 A dependable AMR sensor system for automotive applications Auteurs: Andreina Zambrano, Hans G. Kerkhoff Publié dans: 2017 International Test Conference in Asia (ITC-Asia), 2017, Page(s) 59-64, ISBN 978-1-5386-3051-8 Éditeur: IEEE DOI: 10.1109/ITC-ASIA.2017.8097112 Structured scan patterns retargeting for dynamic instruments access Auteurs: Ahmed Ibrahim, Hans G. Kerkhoff Publié dans: 2017 IEEE 35th VLSI Test Symposium (VTS), 2017, Page(s) 1-6, ISBN 978-1-5090-4482-5 Éditeur: IEEE DOI: 10.1109/VTS.2017.7928955 A cost-efficient dependability management framework for self-aware system-on-chips based on IEEE 1687 Auteurs: Ahmed Ibrahim, Hans G. Kerkhoff Publié dans: 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, Page(s) 1-2, ISBN 978-1-5386-0352-9 Éditeur: IEEE DOI: 10.1109/IOLTS.2017.8046166 Multi-fragment Markov model guided online test generation for MPSoC Auteurs: Vain, Jüri; Tsiopoulos, Leonidas; Kharchenko, Vyacheslav; Kaur, Apneet; Jenihhin, Maksim; Raik, Jaan Publié dans: 2017 Éditeur: ICT in Education, Research and Industrial Applications High-level test generation for processing elements in many-core systems Auteurs: Adeboye Stephen Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik Publié dans: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Page(s) 1-8, ISBN 978-1-5386-3344-1 Éditeur: IEEE DOI: 10.1109/ReCoSoC.2017.8016156 Fault-resilient NoC router with transparent resource allocation Auteurs: Tsotne Putkaradze, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan Publié dans: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Page(s) 1-8, ISBN 978-1-5386-3344-1 Éditeur: IEEE DOI: 10.1109/ReCoSoC.2017.8016161 Run-time reconfigurable instruments for advanced board-level testing Auteurs: Igor Aleksejev, Artur Jutman, Sergei Devadze Publié dans: 2016 IEEE AUTOTESTCON, 2016, Page(s) 1-8, ISBN 978-1-5090-0790-5 Éditeur: IEEE DOI: 10.1109/AUTEST.2016.7589627 Embedded instrumentation toolbox for screening marginal defects and outliers for production Auteurs: Sergei Odintsov, Artur Jutman, Sergei Devadze, Igor Aleksejev Publié dans: 2017 IEEE AUTOTESTCON, 2017, Page(s) 1-9, ISBN 978-1-5090-4922-6 Éditeur: IEEE DOI: 10.1109/AUTEST.2017.8080516 Marginal PCB assembly defect detection on DDR3/4 memory bus Auteurs: Sergei Odintsov, Artur Jutman, Sergei Devadze Publié dans: 2017 IEEE International Test Conference (ITC), 2017, Page(s) 1-10, ISBN 978-1-5386-3413-4 Éditeur: IEEE DOI: 10.1109/TEST.2017.8242070 Synthesis of Admissible Shield Auteurs: Laura Humphrey, Bettina Könighofer, Robert Könighofer, Ufuk Topcu Publié dans: 2017, Page(s) 134-151 Éditeur: Springer International Publishing DOI: 10.1007/978-3-319-49052-6_9 Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects Auteurs: Tino Flenker, Jan Malburg, Gorschwin Fey, Serhiy Avramenko, Massimo Violante, Matteo Sonza Reorda Publié dans: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Page(s) 533-538, ISBN 978-1-5090-6762-6 Éditeur: IEEE DOI: 10.1109/ISVLSI.2017.99 Formal Verification of Masked Hardware Implementations in the Presence of Glitches Auteurs: Roderick Bloem, Hannes Gross, Rinat Iusupov, Bettina Konighofer, Stefan Mangard, and Johannes Winter Publié dans: 2018 Éditeur: EUROCRYPT Intermittent Resistance Fault Detection at Board Level Auteurs: H. Ebrahimi and H.G. Kerkhoff Publié dans: 2018 Éditeur: DDECS On-Chip Lifetime Prediction for Dependable Many-Processor SoCs based on Slack-Delay and IDDX Data Fusion Auteurs: G. Ali, J. Pathrose, Y. Zhao and H.G. Kerkhoff Publié dans: 2018 Éditeur: submitted to International Test Conference Asia (ITC-Asia) IJTAG Compatible Analogue Embedded Instruments for MPSoC Life-time Prediction Auteurs: J.Pathrose, G.Ali, and H. G. Kerkhoff Publié dans: 2018 Éditeur: 2018 19th IEEE Latin American Test Symposium (LATS) Mining Latency Guarantees for RTL Designs Auteurs: Malburg, Jan and Riener, Heinz and Fey, Görschwin Publié dans: 2018 Éditeur: IEEE International Symposium on Multiple-Valued Logic SMT-Based CPS Parameter Synthesis Auteurs: Heinz Riener, Robert Könighofer, Görschwin Fey, and Roderick Bloem (DLR, TU Graz) Publié dans: Applied Verification for Continuous and Hybrid Systems, 2016 Éditeur: ARCH'16 Synchronization, Calibration and Triggering of IEEE 1687 Embedded Instruments Auteurs: A. Jutman, S. Devadze, K. Shibin (Testonica Lab) Publié dans: 2016, Page(s) 1-6 Éditeur: WRTLT’2016 Accessing on-chip temperature health monitors using the IEEE 1687 standard Auteurs: Ali, G. and Badawy, A. and Kerkhoff, H.G. (U.Twente) Publié dans: 2016, Page(s) 776-779 Éditeur: IEEE Circuits & Systems Society A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing Auteurs: Zhao, Yong and Kerkhoff, H.G. (U.Twente) Publié dans: 2016, Page(s) 10-14 Éditeur: IEEE Computer Society Gate-Level Modelling of NBTI-Induced Delays Under Process Variations Auteurs: Copetti, Thiago; Medeiros, Guilherme; Poehls, Leticia; Vargas, Fabian; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan (Tallinn UT) Publié dans: 2016, Page(s) 75-80 Éditeur: IEEE Computer Society Press Counterexample-Guided Diagnosis Auteurs: Heinz Riener and Goerschwin Fey (DLR) Publié dans: 2016 Éditeur: IVSW Synthesizing adaptive test strategies from temporal logic specifications Auteurs: Roderick Bloem, Robert Konighofer, Ingo Pill, Franz Rock Publié dans: 2016 Formal Methods in Computer-Aided Design (FMCAD), 2016, Page(s) 17-24, ISBN 978-0-9835678-6-8 Éditeur: IEEE DOI: 10.1109/FMCAD.2016.7886656 SoCDep²: A framework for dependable task deployment on many-core systems under mixed-criticality constraints Auteurs: Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT) Publié dans: 2016 Éditeur: ReCoSoC Logic-based implementation of fault-tolerant routing in 3D network-on-chips Auteurs: Behrad Niazmand, Siavoosh Payandeh Azad, Jose Flich, Jaan Raik, Gert Jervan, Thomas Hollstein Publié dans: 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2016, Page(s) 1-8, ISBN 978-1-4673-9030-9 Éditeur: IEEE DOI: 10.1109/NOCS.2016.7579317 Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems Auteurs: Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT) Publié dans: 2016 Éditeur: DREAMCloud Online digital compensation Method for AMR sensors Auteurs: Andreina Zambrano, Hans G. Kerkhoff Publié dans: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, Page(s) 1-6, ISBN 978-1-5090-3561-8 Éditeur: IEEE DOI: 10.1109/VLSI-SoC.2016.7753579 Determination of the drift of the maximum angle error in AMR sensors due to aging Auteurs: Andreina Zambrano, Hans G. Kerkhoff Publié dans: 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW), 2016, Page(s) 1-5, ISBN 978-1-5090-2751-4 Éditeur: IEEE DOI: 10.1109/IMS3TW.2016.7524234 WCET overapproximation for software in the context of a Cyber-Physical System Auteurs: Niklas Krafczyk, Heinz Riener, Goerschwin Fey Publié dans: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, Page(s) 1-6, ISBN 978-1-5090-3561-8 Éditeur: IEEE DOI: 10.1109/VLSI-SoC.2016.7753559 Exact diagnosis using boolean satisfiability Auteurs: Heinz Riener, Goerschwin Fey Publié dans: Proceedings of the 35th International Conference on Computer-Aided Design - ICCAD '16, 2016, Page(s) 1-8, ISBN 9781-450344661 Éditeur: ACM Press DOI: 10.1145/2966986.2967036 Multilevel design understanding - from specification to logic invited paper Auteurs: Sandip Ray, Ian G. Harris, Goerschwin Fey, Mathias Soeken Publié dans: Proceedings of the 35th International Conference on Computer-Aided Design - ICCAD '16, 2016, Page(s) 1-6, ISBN 9781-450344661 Éditeur: ACM Press DOI: 10.1145/2966986.2980093 Towards an automated and reusable in-field self-test solution for MPSoCs Auteurs: Ahmed Ibrahim, Hans G. Kerkhoff Publié dans: 2016 28th International Conference on Microelectronics (ICM), 2016, Page(s) 249-252, ISBN 978-1-5090-5721-4 Éditeur: IEEE DOI: 10.1109/ICM.2016.7847862 Efficient utilization of hierarchical iJTAG networks for interrupts management Auteurs: Ahmed Ibrahim, Hans G. Kerkhoff Publié dans: 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016, Page(s) 97-102, ISBN 978-1-5090-3623-3 Éditeur: IEEE DOI: 10.1109/DFT.2016.7684077 Analysis and design of an on-chip retargeting engine for IEEE 1687 networks Auteurs: Ahmed Ibrahim, Hans G. Kerkhoff Publié dans: 2016 21th IEEE European Test Symposium (ETS), 2016, Page(s) 1-6, ISBN 978-1-4673-9659-2 Éditeur: IEEE DOI: 10.1109/ETS.2016.7519301 Thermal issues in test: An overview of the significant aspects and industrial practice Auteurs: J. Alt, P. Bernardi, A. Bosio, R. Cantoro, H. Kerkhoff, A. Leininger, W. Molzer, A. Motta, C. Pacha, A. Pagani, A. Rohani, R. Strasser Publié dans: 2016 IEEE 34th VLSI Test Symposium (VTS), 2016, Page(s) 1-4, ISBN 978-1-4673-8454-4 Éditeur: IEEE DOI: 10.1109/VTS.2016.7477278 Designing reliable cyber-physical systems overview associated to the special session at FDL'16 Auteurs: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Konighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Rock, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao Publié dans: 2016 Forum on Specification and Design Languages (FDL), 2016, Page(s) 1-8, ISBN 979-10-92279-17-7 Éditeur: IEEE DOI: 10.1109/FDL.2016.7880382 Mining Latency Guarantees for RT-level Designs Auteurs: Jan Malburg, Heinz Riener, Goerschwin Fey (DLR) Publié dans: 2017 Éditeur: DUHDe Computing Exact Fault Candidates Incrementally Auteurs: Heinz Riener and Goerschwin Fey (DLR) Publié dans: 2017 Éditeur: DUHDe Mapping Abstract and Concrete Hardware Models for Design Understanding Auteurs: Tino Flenker and Goerschwin Fey (DLR) Publié dans: 2017 Éditeur: DDECS Counterexample-Guided EF Synthesis of Boolean Functions Auteurs: Heinz Riener, Ruediger Ehlers, and Goerschwin Fey (DLR) Publié dans: 2017 Éditeur: MBMV Comprehensive Performance and Robustness Analysis of 2D Turn Models for Network-on-Chips Auteurs: Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT) Publié dans: 2017 Éditeur: ISCAS Automated Area and Coverage Optimization of Minimal Latency Checkers Auteurs: Siavoosh Payandeh Azad, Behrad Niazmand, Apneet Kaur Sandhu, Jaan Raik, Gert Jervan, Thomas Hollstein (Tallinn UT) Publié dans: 2017 Éditeur: IEEE From Online Fault Detection to Fault Management in NoC Routers: A Ground-up Approach Auteurs: Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Adeboye Stephen Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein (Tallinn UT) Publié dans: 2017 Éditeur: DDECS CEGAR-based EF Synthesis of Boolean Functions with an Application to Circuit Rectification Auteurs: Heinz Riener, Rüdiger Ehlers, Görschwin Fey (DLR) Publié dans: 2017 Éditeur: ASP-DAC’17 Property Mining using Dynamic Dependency Graphs Auteurs: Jan Malburg, Tino Flenker, Görschwin Fey (DLR) Publié dans: 2017 Éditeur: ASP-DAC DOI: 10.1109/ASPDAC.2017.7858327 Synthesizing cooperative reactive mission plans Auteurs: Rudiger Ehlers, Robert Konighofer, Roderick Bloem Publié dans: 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), 2015, Page(s) 3478-3485, ISBN 978-1-4799-9994-1 Éditeur: IEEE DOI: 10.1109/IROS.2015.7353862 Immortalizing many-core systems early experiences of the horizon 2020 action IMMORTAL Auteurs: Jaan Raik Publié dans: 2015 International Conference on High Performance Computing & Simulation (HPCS), 2015, Page(s) 561-562, ISBN 978-1-4673-7813-0 Éditeur: IEEE DOI: 10.1109/HPCSim.2015.7237092 On-line Fault Classification and Handling in IEEE1687 based Fault Management System for Complex SoCs Auteurs: K. Shibin, S. Devadze, A. Jutman Publié dans: 2016 Éditeur: IEEE A hybrid algorithm to conservatively check the robustness of circuits Auteurs: Niels Thole, Lorena Anghel, and Goerschwin Fey Publié dans: 2016 Éditeur: IEEE SMT-Based CPS Parameter Synthesis Auteurs: Heinz Riener, Robert Könighofer, Görschwin Fey, and Roderick Bloem Publié dans: 2016 Éditeur: IEEE On-line Monitoring of Maximum Angle Error in AMR Sensors Auteurs: A. Zambrano Publié dans: 2016 Éditeur: IOLTS Matching abstract and concrete hardware models for design understanding Auteurs: Tino Flenker and Goerschwin Fey Publié dans: 2016 Éditeur: IEEE Online Management of Temperature Health Monitors using the IEEE 1687 Standard Auteurs: G. Ali , A. Badewy and H.G. Kerkhoff Publié dans: 2016 Éditeur: IEEE A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers Auteurs: Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan, Gert Jervan, Thomas Hollstein Publié dans: 2015 Euromicro Conference on Digital System Design, 2015, Page(s) 288-292, ISBN 978-1-4673-8035-5 Éditeur: IEEE DOI: 10.1109/DSD.2015.15 Automated minimization of concurrent online checkers for Network-on-Chips Auteurs: Pietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan, Thomas Hollstein Publié dans: 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, Page(s) 1-8, ISBN 978-1-4673-7942-7 Éditeur: IEEE DOI: 10.1109/ReCoSoC.2015.7238079 A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers Auteurs: Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Vineeth Govind, Thomas Hollstein, Gert Jervan, Ranganathan Hariharan Publié dans: Proceedings of the 9th International Symposium on Networks-on-Chip - NOCS '15, 2015, Page(s) 1-8, ISBN 9781-450333962 Éditeur: ACM Press DOI: 10.1145/2786572.2788713 A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage Auteurs: Karputkin, Anton; Raik, Jaan Publié dans: 2016 Éditeur: IEEE New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams Auteurs: Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar Publié dans: 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015, Page(s) 251-254, ISBN 978-1-4799-6780-3 Éditeur: IEEE DOI: 10.1109/DDECS.2015.56 Other (7) Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits Auteurs: Jenihhin, Maksim; Squillero, Giovanni; Copetti, Thiago Santos; Tihhomirov, Valentin; Kostin, Sergei; Gaudesi, Marco; Vargas, Fabian; Raik, Jaan; Sonza Reorda, Matteo; Bolzani Poehls, Leticia; Ubar, Raimund; Medeiros, Guilherme Cardoso Publié dans: Journal of Electronic Testing-Theory and Applications (JETTA), 2016 Éditeur: SPRINGER Semi-Formal Methods for Soft Error Analysis Auteurs: Patrick Klampfl, Robert Könighofer, Roderick Bloem, Ayrat Khalimov, Aiman Abu-Yonis, Shiri Moran Publié dans: 2017 Éditeur: CoRR abs/1712.04291 Designing Reliable Cyber-Physical Systems, Lecture Notes in Electrical Engineering: Languages, Design Methods, and Tools for Electronic System Design Auteurs: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Shlomit Koyfman, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao Publié dans: 2018, Page(s) 15-38 Éditeur: Springer International Publishing DOI: 10.1007/978-3-319-62920-9_2 Design and Implementation of a dependable CPSoC for Automotive Applications Auteurs: G. Ali, H. Ebrahimi, J. Pathrose and H.G. Kerkhoff Publié dans: 2018 Éditeur: submitted to Industrial Cyber-Physical Systems (ICPS) A Flexible Distributed Simulation Environment for Cyber-Physical Systems Using ZeroMQ Auteurs: Ofenloch, Annika and Greif, Fabian Publié dans: Journal of Communications, 2018 Éditeur: Journal of Communications Reliable Health Monitoring and Fault Management Infrastructure based on Embedded Instrumentation and IEEE 1687 Auteurs: A. Jutman, K. Shibin, S. Devadze (Testonica Lab) Publié dans: 2016, Page(s) 240-249 Éditeur: AUTOTESTCON’2016 Learning Models of a Network Protocol using Neural Network Language Models Auteurs: Bernhard Aichernig, Roderick Bloem, Franz Pernkopf, Franz Röck, Tobias Schrank and Martin Tappler (TU Graz) Publié dans: 2016 Éditeur: IEEE Symposium on Security and Privacy Peer reviewed articles (6) Killing strategies for model-based mutation testing Auteurs: Bernhard K. Aichernig, Harald Brandl, Elisabeth Jöbstl, Willibald Krenn, Rupert Schlick, Stefan Tiran Publié dans: Software Testing, Verification and Reliability, Issue 25/8, 2015, Page(s) 716-748, ISSN 0960-0833 Éditeur: John Wiley & Sons Inc. DOI: 10.1002/stvr.1522 Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure Auteurs: Konstantin Shibin, Sergei Devadze, Artur Jutman, Martin Grabmann, Robin Pricken Publié dans: IEEE Design & Test, Issue 34/6, 2017, Page(s) 27-35, ISSN 2168-2356 Éditeur: IEEE Computer Society DOI: 10.1109/MDAT.2017.2750902 Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits Auteurs: Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros Publié dans: Journal of Electronic Testing, Issue 32/3, 2016, Page(s) 273-289, ISSN 0923-8174 Éditeur: Kluwer Academic Publishers DOI: 10.1007/s10836-016-5589-x metaSMT: focus on your application and not on solver integration Auteurs: Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Goerschwin Fey Publié dans: International Journal on Software Tools for Technology Transfer, 2016, ISSN 1433-2779 Éditeur: Springer Verlag DOI: 10.1007/s10009-016-0426-1 Debugging hardware designs using dynamic dependency graphs Auteurs: Jan Malburg, Alexander Finder, Görschwin Fey (DLR) Publié dans: Journal of Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), 2016, ISSN 0141-9331 Éditeur: Elsevier BV Simulating NBTI Degradation in Arbitrary Stressed Analog/Mixed-Signal Environments Auteurs: Jinbo Wan, Hans Kerkhoff, Jaap Bisschop Publié dans: IEEE Transactions on Nanotechnology, 2016, Page(s) 1-1, ISSN 1536-125X Éditeur: Institute of Electrical and Electronics Engineers DOI: 10.1109/TNANO.2015.2505092 Book chapters (3) Energy Efficient Multi-Fragment Markov Model Guided Online Model-Based Testing for MPSoC Auteurs: Vain,Jüri; Tsiopoulos, Leonidas; Kharchenko, Vyacheslav; Kaur, Apneet; Jenihhin, Maksim; Raik, Jaan; Nõmm Sven Publié dans: Green-IT Engineering: Social, Business and Industrial Applications (1−21), 2018 Éditeur: Springer Cooperative Reactive Synthesis Auteurs: Roderick Bloem, Rüdiger Ehlers, Robert Könighofer Publié dans: Automated Technology for Verification and Analysis, 2015, Page(s) 394-410, ISBN 978-3-319-24953-7 Éditeur: Springer International Publishing DOI: 10.1007/978-3-319-24953-7_29 Case Study: Automatic Test Case Generation for a Secure Cache Implementation Auteurs: Roderick Bloem, Daniel Hein, Franz Röck, Richard Schumi Publié dans: Tests and Proofs, 2015, Page(s) 58-75, ISBN 978-3-319-21215-9 Éditeur: Springer International Publishing DOI: 10.1007/978-3-319-21215-9_4 Droits de propriété intellectuelle Patent (2) ASSURING CHIP RELIABILITY WITH AUTOMATIC GENERATION OF DRIVERS AND ASSERTIONS Numéro de demande/publication: US 9483591 Date: 2015-11-27 ASSURING CHIP RELIABILITY WITH AUTOMATIC GENERATION OF DRIVERS AND ASSERTIONS Numéro de demande/publication: US 9483591 Date: 2015-11-27 Recherche de données OpenAIRE... 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