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PULLing the limits of NANOCmos electronics


PULLNANO is a 30-month IP proposal for a powerful project focused on advanced RTD activities to push forward the limits of CMOS technologies. PULLNANO focuses on the development of 32 and 22nm CMOS technology nodes opening the way to the long term future of these technologies.

The 1st objective of the project, to be achieved at t0+24, is the feasibility demonstration of 32nm node Front-End and Back-End process modules through a very aggressive SRAM chip and a multilevel metal stack structure.

The 2nd objective is to realize research on the materials, devices, architectures, interconnects modeling and characterization to prepare the future 22nm node. For this purpose, PULLNANO incorporates an unprecedented number of Academic teams organized in clusters.

The 3rd objective is to establish a common action between technology and design people in order to assess the technologies in terms of performances and power consumption.

The 4th objective is to define, through a forum of European equipment suppliers, the specifications of future advanced process, characterization and metrology equipments. PULLNANO starts from the ongoing, very successful, NANOCMOS project focused on the 45nm technology.

The original Consortium is enlarged to gather the best European competences in the domain. PULLNANO establishes close relation with the MEDEA+ programmes, where PULLNANO results are developed towards the industrial exploitation phase. This cooperation optimizes European funding while avoiding overlaps. PULLNANO adopts a professional management structure that deals with the complexity and ambitions of the project. PULLNANO is a reference project and a unique opportunity to increase the worldwide impact of European Nanoelectronics and create the conditions for future IST application.

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IP - Integrated Project


29 boulevard romain rolland
92120 Montrouge

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