In WP1, CQD-MIG diode arrays and ferroelectric memory arrays were integrated on top of CMOS circuits in back end of line (BEOL) process. First, vias were etched and filled to gain contacts to the CMOS circuits, and then metal layer structures were added to serve as bottom electrodes for the post-processed devices. For CQD-MIG sensor the thickness of that layer was optimized for graphene deposition. Sets of PbS, PbS/CdS, and lead-free InAs nanoparticles were synthesized and their application on the MIG diodes was improved by structuring the nanoparticle layer. Images taken by the CQD-MIG sensor array show photodetection capabilities. For FeRAM devices, the bottom electrode required development of a special process to achieve high-stress TiN film with specific crystal orientation to enhance the ferroelectricity of the next layer. The integration of ferroelectric Hf0.5Zr0.5O2 (HZO) on CMOS was performed in BEOL and characterized with focus on memory state dynamics. The different area ratios between the HZO capacitor and the CMOS yield different dynamics, enabling application-driven solutions. Analog memory states were achieved with pulsed writing methods, showing good retention (measured to 1e3 sec., extrapolated to >1 year). Full arrays of CMOS FeFETs were implemented and are currently under measurements. According to simulations, combining CMOS and FeFETs can provide CNN weights with 5-bits resolution. The FeFET integration process was transferred from ULUND to VTT, where a proof-of-concept FeFETs were integrated. VTT has now the capability to integrate FeCaps on 8” wafers. Good performance and high wafer uniformity has been demonstrated on 6” wafers and similar device tests are already planned for 8” wafers.
In WP2 neuromorphic circuits that gain performance from massive parallelism and computing topology were implemented. Several integrated circuits were taped-out (jointly with WP3) including CQD-MIG sensor readout circuit, associative memory, convolution accelerator, and HDC arrays. Cellular and cerebellar processors were put on the same chip to take advantage of high-speed on-chip data buses. The sensor front-end accommodates data path for both CMOS and CQD-MIG pixels. The processing hardware provides temporal difference events and fixed-pattern noise (FPN)-compensated intensity images. This data is used to generate complex events that compactly describe spatial and temporal features. The complex events are used for interest point detection, optical flow computation, and motion pattern extraction using an associative processor. On-chip cellular neural net provides means for segmentation, clustering, and region of interest (ROI). A chip-to-chip link between cellular/cerebellar and cortical processors collects and transfers ROI data. On-chip controllers (custom and RISC-V) support large-scale real-time system operation and communication.
WP3 tackled higher-level information processing and system integration. The designed cortical processor, comprising a DNN for region of interest (ROI) detection and feature extraction, and a HDC model for sequence classification, shows a very low power consumption. The chip controlled by on-chip RISC-V contains two data paths: one consisting of a DNN and an HDC blocks in CMOS technology, and the other comprises a DNN combining CMOS with FeFETs and a CMOS-only HDC block. Studies on gesture recognition have shown that hypervectors with 2048 components and DNNs with 5 bits of resolution provide sufficient accuracy. This eases hardware requirements, and thus its implementation as an edge device. A digital twin of the system supports hardware-realistic algorithm evaluation and co-design in WP2, WP3, and WP4.
WP4 evaluated the sensor layer, the computational layer, and the entire system in selected applications. The use-case was defined in parallel to the development of the components, taking into account predicted hardware capabilities and legal issues. Evaluation criteria were defined, an evaluation corpus (dataset) was developed, and a comparative evaluation was done between algorithms applied on the original corpus data and the data from HW-realistic sensor emulator.
