Ferroelectric Vertical Low energy Low latency low volume Modules fOr Neural network Transformers In 3D

Project Information

FVLLMONTI

Grant agreement ID: 101016776

DOI

10.3030/101016776

Project closed

EC signature date 1 December 2020

Start date 1 January 2021

End date 31 August 2025

Funded under

• EXCELLENT SCIENCE - Future and Emerging Technologies (FET)

Total cost

€ 4 760 060,00

EU contribution

€ 4 760 060,00

Coordinated by

UNIVERSITE DE BORDEAUX
France

Periodic Reporting for period 3 - FVLLMONTI (Ferroelectric Vertical Low energy Low latency low volume Modules fOr Neural network Transformers In 3D)

Reporting period: 2024-03-01 to 2025-08-31

Summary of the context and overall objectives of the project

Current neural machine translation systems rely on very large neural networks (NNs) that require high computing power and must run on remote servers. This creates latency, increases energy consumption, and raises privacy concerns when speech data must be sent online. These constraints make real-time speech translation difficult and often incompatible with sensitive data.
FVLLMONTI brings together expertise in nanoelectronics, unconventional logic design, reliability, system-level design, neural machine translation and cognitive sciences to create a lightweight in-ear device able to perform speech-to-speech translation without an internet connection.
The main limitation comes from conventional 2D electronic architectures, whose interconnects do not scale and remain far less efficient than biological neural systems. FVLLMONTI aims to overcome these limits by using Vertical Nanowire Field-Effect Transistors (VNWFETs) to enable compact and energy-efficient 3D neuromorphic computing.
The project therefore focuses on fabricating VNWFETs, establishing a design-technology co-optimization (DTCO) flow for 3D stacked neural hardware, and developing hardware-software co-optimization methods to support energy-efficient translation with minimal accuracy loss.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

At the beginning of the project, efforts focused on establishing effective collaboration workflows within the consortium. Two major coordinated activities were structured: the DTCO loop and the Hardware-Software (Hw-Sw) loop.
In the DTCO loop, several variants of the VNWFET technology were fabricated, measured and benchmarked. A complete simulation flow was set up, including static logic libraries for different junctionless technologies. Multiple Compute Cube Neural Network (N2C2) blocks were synthesized up to 32-bit widths, including a 4-bit version used to validate the full physical-design flow. A multi-scale reliability-aware framework was also developed to quantify thermal, voltage and aging effects on VNWFET-based circuits.
In the Hw-Sw loop, the gem5-X full-system simulator was extended with loosely and tightly coupled accelerators compatible with N2C2. This enabled execution of Automated Speech Recognition (ASR) and Machine Translation (MT) workloads. Application work focused on resource-aware optimizations such as quantization, pruning and sparsity techniques adapted to N2C2 characteristics.
Key outcomes include the open-source release of the parameterizable simulator with application examples, integration of emotion recognition for FVLLMONTI use cases, delivery of an architectural library including thermal models and design trade-offs, and co-optimization of hardware and neural network architectures for ASR and MT.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

Computing needs continue to grow, especially for embedded AI applications that require low-latency, secure and energy-efficient processing close to the data source. Excellent energy efficiency is therefore essential. VNWFET technology enables a transition from 2D to truly 3D architectures, offering major gains in density and speed.
New computing paradigms based on such emerging technologies have so far received limited industrial traction due to insufficient proof of feasibility. FVLLMONTI addresses this gap by demonstrating a proof-of-concept computing system combining VNWFET devices with an innovative 3D NN architecture (N2C2). This constitutes a major advance and provides new insights in device fabrication, modelling, logic techniques, neural architectures and language technologies.
The results are expected to stimulate large-scale European research and industrial investment in beyond-CMOS technologies and advanced DTCO approaches. Measurements performed on real VNWFET variants confirm that these devices and associated 3D NN architectures are ultra-fast, dense and energy-efficient, opening the way to new information-processing and data-storage paradigms. FVLLMONTI therefore contributes to meeting society’s growing need for secure, low-energy and high-performance communication technologies.

Overview of the FVLLMONTI work packages and interactions between them