A key priority at the beginning of the project was to develop appropriate operating methods in order to guarantee and sustain the quality of interactions whithin the consortium. Within the FVLLMONTI project framework, two dense and intense collaborative activities have been structured to secure the success of the two main collective efforts: The Design-Technology-Co-Optimization (DTCO) loop and the Hardware-Software (Hw-Sw) loop. With respect to the DTCO loop, unlike the conventional value chain of micro/nano-electronics where interactions and software tools between device (transistor), measurements, compact modelling and circuit activities have been settled for decades to achieve the Von Neumann machine, the FVLLMONTI value chain is in its early stages aiming to achieve an optimal neural network structure. Because the overall technology achievement towards this 3D matrix structure is the Compute Cube Neural Network (N2C2) definition, the careful settlement of DTCO loop interactions has been a priority. Several variants of the vertical Nanowire FET technology are expected in term of junctionless devices, ambipolar devices, number of stacked gates, and ferroelectric gates. During this period, a nomenclature of these variants has been established to ease the dialogue between partners. As for the Hw-Sw loop, the main aim is the co-design of hardware-software architectures, systems and applications leveraging the novel devices characterized in the DTCO loop. The goal is to devise efficient, yet flexible architectural templates, in order to enable systematic design space explorations of different configurations, array sizes, supported data representations and operations. During this period, we extended the gem5-X full-system simulator, defining extensions as loosely and tightly coupled accelerators. These are defined as behavioural modules by designing their interface and event-based behavior, considering the internal implementation of the implemented functionality as a black-box, focusing on accelerator integration. The virtual N2C2-capable systems defined in gem5-X will be able to execute the Automated Speech Recognition (ASR) and Machine Translation (ML) applications. Application-related efforts focused on resource-aware optimization, starting from state-of-the-art approaches such as quantization and pruning of low-relevance parts of Transformer models, but building on top of them to gauge the additional benefits deriving from hardware-aware (and, in particular, N2C2-aware) approaches, including sparsity considerations among others.