Periodic Reporting for period 1 - SIPHO-G (Advanced GeSi components for next-generation silicon photonics applications)
Période du rapport: 2021-01-01 au 2022-12-31
By developing 100Gbaud Germanium-Silicon (GeSi) Quantum-Confined Stark-Effect (QCSE) modulators and highly sensitive 100Gbaud avalanche photodetectors (APD), SIPHO-G will bring breakthrough optical modulation and photodetection capability to the world of Silicon Photonics. The newly developed compact, waveguide-coupled modulator and detector building blocks will be monolithically integrated in a high-yield cutting-edge 300mm Silicon Photonics platform, propelling the bandwidth density, power efficiency, sensitivity and complexity of silicon photonic integrated circuits to the next level. Supported by an elaborate simulation and design enablement framework, SIPHO-G will demonstrate an extensive set of application-driven prototypes across the O-band and C- band. By bringing together the entire Silicon Photonics value chain, SIPHO-G will accelerate the development of next-generation co-packaged optics, long-haul optical communications, as well as emerging Photonic Integrated Circuit (PIC) applications such as optical neuromorphic computing, with performance levels of 4x-20x beyond current state-of-the-art.
n general the project is running well, collaborations among partners are in place and ongoing, and it is on track to achieve the goal set in the description of action (DoA). The project management (WP1) implemented monthly calls to track the project progress, a first face-to-face consortium meeting took place end 2022 at imec, after meeting several times via teleconference, and reporting was prepared (D1.1 First project activity report and the first periodic report). Due to a delay in design of the PIC component, an extension of the project by six months was requested and approved through Amendment 1.
In WP2 the development of frameworks to model optical properties of QCSE and APDs is ongoing at nextnano and IMEC, and an initial PDK was completed by LUCEDA. Nextnano’s QCSE model was tested against the samples provided by IMEC and deliverable D2.1 “Report on device modelling and PDK” was submitted. WP2 has a slight delay with T2.1 that will be compensated with the extension of the project.
Processing development to optimize the epitaxial growth for QCSE and APD devices in WP3 is ongoing according to schedule for APD devices and QCSE modulators operating in O-band (IMEC). The work on the C-band modulators by AMBEL is slightly delayed but picked-up by the end of 2022. A revision of deliverable D3.1 “Report on the epitaxial growth development for QCSE modulators and for APDs” has been resubmitted.
The integration of these components in the silicon photonics integration platform is ongoing at IMEC and designs of integrated components are included in the PIC design vehicle. In WP4 measurements of device parameters and evaluation of their performance is ongoing. A few issues occurred on integrating the components into the photonics platform which led to a delay in processing of the QCSE samples. Mitigations have been identified and will be implemented in Run #2. Therefore, the deliverable D4.1 “Report on building block development from Run #1” is also delayed.
In WP5 the SIPHO-G Demonstrator Run #1 is completed. The first demonstrator circuits have been designed, fabricated and assembled together with the first generation Electronic Integrated Circuit (EIC) that has been designed by GF. Testing of the assembled demonstrators will be performed by MLNX and Ericsson. The work on the demonstrators is on track, the principle of operation of the EAM-based multi-level transmitter and coherent transmitter, respectively, was investigated in circuit-level simulations by MLNX, Ericsson worked on the transceiver specifications and started the study for the design and realization of the fronthaul networks demonstrators, and AUTH has developed a mathematical framework towards investigating the scalability credentials of the proposed crossbar architecture. The deliverable D5.1 “Specifications of transceiver modules and design report of Run #1” was submitted and D5.2 “Testbed development, definition of testing methodologies and test plan” will be submitted with a few months delay.
The Dissemination, exploitation and innovation management (WP6) is ongoing. Dissemination material (templates, website, ...) as well as exploitation and innovation content were on time. SIPHO-G results have been published in about 10 scientific conferences/journals and a plan for future publications has been prepared. The exploitable results have been identified during the first 12 months and are being verified and updated every 6 months. The list of exploitable results and their descriptions together with communication and dissemination activities are part of deliverable D6.1 that has been submitted with a few months delay.
In WP2 the development of frameworks to model optical properties of QCSE and APDs is ongoing at nextnano and IMEC, and an initial PDK was completed by LUCEDA. Nextnano’s QCSE model was tested against the samples provided by IMEC and deliverable D2.1 “Report on device modelling and PDK” was submitted. WP2 has a slight delay with T2.1 that will be compensated with the extension of the project.
Processing development to optimize the epitaxial growth for QCSE and APD devices in WP3 is ongoing according to schedule for APD devices and QCSE modulators operating in O-band (IMEC). The work on the C-band modulators by AMBEL is slightly delayed but picked-up by the end of 2022. A revision of deliverable D3.1 “Report on the epitaxial growth development for QCSE modulators and for APDs” has been resubmitted.
The integration of these components in the silicon photonics integration platform is ongoing at IMEC and designs of integrated components are included in the PIC design vehicle. In WP4 measurements of device parameters and evaluation of their performance is ongoing. A few issues occurred on integrating the components into the photonics platform which led to a delay in processing of the QCSE samples. Mitigations have been identified and will be implemented in Run #2. Therefore, the deliverable D4.1 “Report on building block development from Run #1” is also delayed.
In WP5 the SIPHO-G Demonstrator Run #1 is completed. The first demonstrator circuits have been designed, fabricated and assembled together with the first generation Electronic Integrated Circuit (EIC) that has been designed by GF. Testing of the assembled demonstrators will be performed by MLNX and Ericsson. The work on the demonstrators is on track, the principle of operation of the EAM-based multi-level transmitter and coherent transmitter, respectively, was investigated in circuit-level simulations by MLNX, Ericsson worked on the transceiver specifications and started the study for the design and realization of the fronthaul networks demonstrators, and AUTH has developed a mathematical framework towards investigating the scalability credentials of the proposed crossbar architecture. The deliverable D5.1 “Specifications of transceiver modules and design report of Run #1” was submitted and D5.2 “Testbed development, definition of testing methodologies and test plan” will be submitted with a few months delay.
The Dissemination, exploitation and innovation management (WP6) is ongoing. Dissemination material (templates, website, ...) as well as exploitation and innovation content were on time. SIPHO-G results have been published in about 10 scientific conferences/journals and a plan for future publications has been prepared. The exploitable results have been identified during the first 12 months and are being verified and updated every 6 months. The list of exploitable results and their descriptions together with communication and dissemination activities are part of deliverable D6.1 that has been submitted with a few months delay.
SIPHO-G brings together a comprehensive consortium that will complement today’s SiPho toolbox with the much desired advanced modulator and photodetector building blocks, in the form of the waveguide-integrated Quantum-Confined Stark Effect (QCSE) modulator, and Separate-Absorption-Charge-Multiplication (SACM) APDs. Both devices will be implemented using wafer-scale monolithic epitaxial growth of highly crafted Ge/Si layer stacks, using chemical-vapor deposition (CVD) epitaxial reactors already available in mainstream CMOS foundries, guaranteeing straightforward introduction into future products by leveraging existing supply chains. In order to demonstrate the full potential of the newly developed components at the transceiver subsystem level, SIPHO-G will also build a 1.6T hybrid module prototype, including both the advanced SiPho PIC and a carefully co-designed EIC chip containing high-speed driver and amplifier arrays implemented in advanced FDX22 technology, which is ideally suited for high-speed transceivers. This demonstrator module, fully manufactured in Europe, will showcase the capability of the newly developed technology at a higher abstraction level and fast-track the industrial uptake.
After 24 months in the project, a 1st run is completed and being characterized as we speak. All supporting activities (from the PDK, over to the demonstrator and its testing activities) are ongoing, and continuing on the path of completion.
After 24 months in the project, a 1st run is completed and being characterized as we speak. All supporting activities (from the PDK, over to the demonstrator and its testing activities) are ongoing, and continuing on the path of completion.