Below, we summarize our progress towards achieving the key objectives.
Objective 1: Achieve 100x improvement in energy efficiency.
To achieve 100x improvement in energy-efficiently, we have developed an Ultra-Low-Power (ULP) library with novel architectural and micro-architectural accelerator building blocks, in short ULP blocks, having common or standard interfaces, and optimized at micro-architecture, circuit, and device levels. The developed ULP blocks uses different architectural paradigms, such as Compute-in-Memory (CIM), Compute Near Memory (CNM), and Coarse-Grained Reconfigurable Arrays (CGRA), with each of them tailored to benefit a specific use-case to achieve the highest energy-efficiency. So far we have successfully demonstrated the functional operation of the ULP accelerators on simulation-level and currently we are working towards a hardware prototype for energy-efficiency measurements.
Objective 2: Reduce design time by 10x.
To reduce the design time by 10x we developed 1) A Transparent and compositional programming flow and 2) A compositional architecture Design-Space Exploration (DSE) and SoC generation tool flow. We have built the front-end compilation chain, targeting both MLIR and LLVM IR. At the code generation front, our domain-specific compiler lowers operations to custom RISC-V ISA accelerator extensions. We have also contributed to the IREE OSS ML compiler framework, having developed an ONNX importer that converts ONNX modules to Torch MLIR for IREE compilation. We have introduced a scalable cache model for ML (affine-heavy) programs, significantly reducing analysis time and enabling efficient updates after program modifications. For secure compilation, we have facilitated peephole rewrite validation at the intermediate representation level by automating integration with interactive theorem provers. For the automated DSE and SoC generation, we have developed a multi-accelerator architecture simulator, Stream, to analytically study optimal SoC architectures.
Objective 3: Provide hardware security.
We identified relevant attack scenarios by including side-channel attacks based on physical access to the device, mutually distrustful applications on a single device and even powerful attackers with access to large-scale quantum computers. To account for this wide range of attack scenarios, we were working on different interrelated frontiers: Trusted Execution Environments (TEE), Post-quantum cryptography (PQC), and security of compute-in-memory (CIM). We have a working prototype of TEE based on Keystone and the Rocket core. We have conducted a careful exploration of PQC schemes to determine the best fit for the specific needs of Convolve. On the CIM frontier, we are able to extract neural network weights from the crossbars via power side-channels and are working on effective countermeasures.
Objective 4: Enable smart edge applications.
We have laid the groundwork for edge application use-case by defining requirements and benchmarks for smart edge processors. Initial point demos were prepared to guide target adjustments, supporting technical work package topics with application-focused approach. Key achievements include delivering application code bases, and pushing the state-of-the-art research on quantization, efficient deployment of neural networks for resource efficient speech quality prediction, acoustic scene analysis and image processing applications.
