A multiprocessor system on chip with in-memory neural processing unit

Información del proyecto

NeuroSoC

Identificador del acuerdo de subvención: 101070634

DOI

10.3030/101070634

Fecha de la firma de la CE 20 Junio 2022

Fecha de inicio 1 Septiembre 2022

Fecha de finalización 28 Febrero 2026

Financiado con arreglo a

• Digital, Industry and Space

Coste total

€ 7 952 677,50

Aportación de la UE

€ 7 952 677,00

Coordinado por

STMICROELECTRONICS SRL
Italy

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Resultado final

Documents, reports (6)

Competitors, benchmarsk and KPIs report

Competitor benchmarking report and Benchmark documentation data and KPIs

Report on AI optimized ISA extensions
Public communication activities - first year

Public communication activities first year

Public communication activities - second year
Tool-flow for performance evaluation

Toolflow for performance evaluation NeuroSoc competition

RISC-V co-processor unit for IMNPU specifications, functional safe RISC-V host core specifications

RISCV coprocessor unit for IMNPU specifications functional safe RISCV host core specifications

Publicaciones

Peer reviewed articles (4)

Exploiting the State Dependency of Conductance Variations in Memristive Devices for Accurate In-Memory Computing

Autores: Athanasios Vasilopoulos, Julian Buchel, Benedikt Kersting, Corey Lammie, Kevin Brew, Samuel Choi, Timothy Philip, Nicole Saulnier, Vijay Narayanan, Manuel Le Gallo, Abu Sebastian
Publicado en: IEEE Transactions on Electron Devices, 2023, ISSN 1557-9646
Editor: IEEE
DOI: 10.1109/TED.2023.3321014

Designing Circuits for AiMC Based on Non-Volatile Memories: a Tutorial Brief on Trade-offs and Strategies for ADCs and DACs Co-design

Autores: Vignali, Ricardo; Zurla, R; Pasotti, Marco; Rolandi, P. L; Singh, A.; Le Gallo, Manuel; Sebastian, Abu; Jang, Taekwang; Antolini, Alessio; FRANCHI SCARSELLI, Eleonora; Cabrini, Alessandro
Publicado en: IEEE Transactions on Circuits and Systems, 2024, ISSN 1558-0806
Editor: IEEE
DOI: 10.1109/tcsii.2023.3340112

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing

Autores: Francesco Conti; Gianna Paulin; Angelo Garofalo; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggiman; Hayate Okuhara; Luca Benini
Publicado en: IEEE Journal of Solid-State Circuits, 59 (1), 2024, ISSN 1558-173X
Editor: IEEE
DOI: 10.48550/arxiv.2305.08415

RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Acceleration

Autores: TORTORELLA, Yvan; Bertaccini, Luca; BENINI, LUCA; ROSSI, Davide; Conti, Francesco
Publicado en: Future Generation Computer Systems, 2023, ISSN 0167-739X
Editor: Future Generation Computer Systems
DOI: 10.48550/arxiv.2301.03904

Conference proceedings (5)

ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers

Autores: İslamoğlu, Gamze; Scherer, Moritz; Paulin, Gianna; Fischer, Tim; Jung, Victor J.B.; Garofalo, Angelo; BENINI, LUCA
Publicado en: 2023 ACM/IEEE International Symposium on Low Power Electronics and Design, 2023, ISBN 978-1-4503-9354-6
Editor: IEEE
DOI: 10.3929/ethz-b-000638984

A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing

Autores: Ferro, Elena; Vasilopoulos, Athanasios; Lammie, Corey; Gallo, Manuel Le; Benini, Luca; Boybat, Irem; Sebastian, Abu
Publicado en: 2024 IEEE International Symposium, 2024, ISBN 979-8-3503-3099-1
Editor: 2024 IEEE International Symposium
DOI: 10.48550/arxiv.2402.07549

WIP: Automatic DNN Deployment on Heterogeneous Platforms: the GAP9 Case Study

Autores: Luka Macan; Alessio Burrello; Luca Benini; Francesco Conti
Publicado en: 2023 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2023, ISSN 2643-1726
Editor: IEEE
DOI: 10.1145/3607889.3609092

A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks

Autores: Nadalini, Alessandro; Rutishauser, Georg; Burrello, Alessio; Bruschi, Nazareno; Garofalo, Angelo; Benini, Luca; Conti, Francesco; Rossi, Davide
Publicado en: 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2023, ISBN 979-8-3503-2769-4
Editor: IEEE
DOI: 10.48550/arxiv.2307.01056

xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems

Autores: Georg Rutishauser, Joan Mihali, Moritz Scherer, Luca Benini
Publicado en: IEEE Application-specific Systems, Architectures and Processors, 2024, ISSN 2160-0511
Editor: IEEE

Other (3)

Spiking Neural Networks in the Alexiewicz Topology: A New Perspective on Analysis and Error Bounds

Autores: Moser, Bernhard A.; Lunglmayr, Michael
Publicado en: 2023
Editor: preprint
DOI: 10.48550/arxiv.2305.05772

On Leaky-Integrate-and Fire as Spike-Train-Quantization Operator on Dirac-Superimposed Continuous-Time Signals

Autores: Moser, Bernhard A.; Lunglmayr, Michael
Publicado en: 2024
Editor: PREPRINT
DOI: 10.48550/arxiv.2402.07954

Use of RISC-V to develop multiprocessor host subsystems for accelerated platform with In Memory computing based on NVM memories for AI inference answering functional safety requirements for industrial and automotive applications

Autores: Giulio Urlini and all partners
Publicado en: 2024
Editor: RISC-V SUMMIT