A multiprocessor system on chip with in-memory neural processing unit

Informations projet

NeuroSoC

N° de convention de subvention: 101070634

DOI

10.3030/101070634

Date de signature de la CE 20 Juin 2022

Date de début 1 Septembre 2022

Date de fin 28 Février 2026

Financé au titre de

• Digital, Industry and Space

Coût total

€ 7 952 677,50

Contribution de l’UE

€ 7 952 677,00

Coordonné par

STMICROELECTRONICS SRL
Italy

CORDIS fournit des liens vers les livrables publics et les publications des projets HORIZON.

Les liens vers les livrables et les publications des projets du 7e PC, ainsi que les liens vers certains types de résultats spécifiques tels que les jeux de données et les logiciels, sont récupérés dynamiquement sur OpenAIRE .

Livrables

Documents, reports (6)

Competitors, benchmarsk and KPIs report

Competitor benchmarking report and Benchmark documentation data and KPIs

Report on AI optimized ISA extensions
Public communication activities - first year

Public communication activities first year

Public communication activities - second year
Tool-flow for performance evaluation

Toolflow for performance evaluation NeuroSoc competition

RISC-V co-processor unit for IMNPU specifications, functional safe RISC-V host core specifications

RISCV coprocessor unit for IMNPU specifications functional safe RISCV host core specifications

Publications

Peer reviewed articles (5)

Exploiting the State Dependency of Conductance Variations in Memristive Devices for Accurate In-Memory Computing

Auteurs: Athanasios Vasilopoulos, Julian Buchel, Benedikt Kersting, Corey Lammie, Kevin Brew, Samuel Choi, Timothy Philip, Nicole Saulnier, Vijay Narayanan, Manuel Le Gallo, Abu Sebastian
Publié dans: IEEE Transactions on Electron Devices, 2023, ISSN 1557-9646
Éditeur: IEEE
DOI: 10.1109/TED.2023.3321014

IEEE Design and Test

Auteurs: Philip Wiese; Gamze İslamoğlu; Moritz Scherer; Luka Macan; Victor Jean-Baptiste Jung; Alessio Burrello; Francesco Conti; Luca Benini
Publié dans: IEEE Design & est, 2025, ISSN 2168-2356
Éditeur: IEEE Design & Test
DOI: 10.48550/ARXIV.2408.02473

Designing Circuits for AiMC Based on Non-Volatile Memories: a Tutorial Brief on Trade-offs and Strategies for ADCs and DACs Co-design

Auteurs: Vignali, Ricardo; Zurla, R; Pasotti, Marco; Rolandi, P. L; Singh, A.; Le Gallo, Manuel; Sebastian, Abu; Jang, Taekwang; Antolini, Alessio; FRANCHI SCARSELLI, Eleonora; Cabrini, Alessandro
Publié dans: IEEE Transactions on Circuits and Systems, 2024, ISSN 1558-0806
Éditeur: IEEE
DOI: 10.1109/tcsii.2023.3340112

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing

Auteurs: Francesco Conti; Gianna Paulin; Angelo Garofalo; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggiman; Hayate Okuhara; Luca Benini
Publié dans: IEEE Journal of Solid-State Circuits, 59 (1), 2024, ISSN 1558-173X
Éditeur: IEEE
DOI: 10.48550/arxiv.2305.08415

RedMule: A Mixed-Precision Matrix-Matrix Operation Engine for Flexible and Energy-Efficient On-Chip Linear Algebra and TinyML Training Acceleration

Auteurs: TORTORELLA, Yvan; Bertaccini, Luca; BENINI, LUCA; ROSSI, Davide; Conti, Francesco
Publié dans: Future Generation Computer Systems, 2023, ISSN 0167-739X
Éditeur: Future Generation Computer Systems
DOI: 10.48550/arxiv.2301.03904

Book chapters (2)

On the Sampling Sparsity of Neuromorphic Analog-to-Spike Conversion based on Leaky Integrate-and-Fire

Auteurs: Moser, Bernhard A.; Lunglmayr, Michael
Publié dans: 2024, ISSN 2634-4386
Éditeur: Neuromorphic Computing and Engineering
DOI: 10.48550/ARXIV.2410.17441

On the sampling sparsity of analog-to-spike conversion based on leaky integrate-and-fire

Auteurs: Bernhard A Moser; Michael Lunglmayr
Publié dans: Neuromorphic Computing and Engineering, 2025, ISSN 2634-4386
Éditeur: Neuromorphic Computing and Engineering
DOI: 10.1088/2634-4386/ADB884

Conference proceedings (8)

ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers

Auteurs: İslamoğlu, Gamze; Scherer, Moritz; Paulin, Gianna; Fischer, Tim; Jung, Victor J.B.; Garofalo, Angelo; BENINI, LUCA
Publié dans: 2023 ACM/IEEE International Symposium on Low Power Electronics and Design, 2023, ISBN 978-1-4503-9354-6
Éditeur: IEEE
DOI: 10.3929/ethz-b-000638984

A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing

Auteurs: Ferro, Elena; Vasilopoulos, Athanasios; Lammie, Corey; Gallo, Manuel Le; Benini, Luca; Boybat, Irem; Sebastian, Abu
Publié dans: 2024 IEEE International Symposium, 2024, ISBN 979-8-3503-3099-1
Éditeur: 2024 IEEE International Symposium
DOI: 10.48550/arxiv.2402.07549

Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers

Auteurs: Moritz Scherer; Luka Macan; Victor J. B. Jung; Philip Wiese; Luca Bompani; Alessio Burrello; Francesco Conti; Luca Benini
Publié dans: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024
Éditeur: ESWEEK - CASES 2024
DOI: 10.48550/ARXIV.2408.04413

WIP: Automatic DNN Deployment on Heterogeneous Platforms: the GAP9 Case Study

Auteurs: Luka Macan; Alessio Burrello; Luca Benini; Francesco Conti
Publié dans: 2023 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2023, ISSN 2643-1726
Éditeur: IEEE
DOI: 10.1145/3607889.3609092

Specialization meets Flexibility: a Heterogeneous Architecture for High-Efficiency, High-flexibility AR/VR Processing

Auteurs: Prasad, AS; Benini, L; Conti, F
Publié dans: 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, ISBN 979-8-3503-2348-1
Éditeur: IEEE Press
DOI: 10.3929/ETHZ-B-000639835

A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks

Auteurs: Nadalini, Alessandro; Rutishauser, Georg; Burrello, Alessio; Bruschi, Nazareno; Garofalo, Angelo; Benini, Luca; Conti, Francesco; Rossi, Davide
Publié dans: 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2023, ISBN 979-8-3503-2769-4
Éditeur: IEEE
DOI: 10.48550/arxiv.2307.01056

On the Solvability of the {XOR} Problem by Spiking Neural Networks

Auteurs: Moser, Bernhard A.; Lunglmayr, Michael
Publié dans: 2024
Éditeur: Communications in Computer and Information Science ((CCIS,volume 2169))
DOI: 10.48550/ARXIV.2408.05845

xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems

Auteurs: Georg Rutishauser, Joan Mihali, Moritz Scherer, Luca Benini
Publié dans: IEEE Application-specific Systems, Architectures and Processors, 2024, ISSN 2160-0511
Éditeur: IEEE

Other (4)

TOOL-FLOW FOR PERFORMANCE EVALUATION

Auteurs: Theodore Antonakopoulos; Iain Keaney
Publié dans: 2023
Éditeur: NEUROSOC
DOI: 10.5281/ZENODO.8192699

Spiking Neural Networks in the Alexiewicz Topology: A New Perspective on Analysis and Error Bounds

Auteurs: Moser, Bernhard A.; Lunglmayr, Michael
Publié dans: 2023
Éditeur: preprint
DOI: 10.48550/arxiv.2305.05772

On Leaky-Integrate-and Fire as Spike-Train-Quantization Operator on Dirac-Superimposed Continuous-Time Signals

Auteurs: Moser, Bernhard A.; Lunglmayr, Michael
Publié dans: 2024
Éditeur: PREPRINT
DOI: 10.48550/arxiv.2402.07954

Use of RISC-V to develop multiprocessor host subsystems for accelerated platform with In Memory computing based on NVM memories for AI inference answering functional safety requirements for industrial and automotive applications

Auteurs: Giulio Urlini and all partners
Publié dans: 2024
Éditeur: RISC-V SUMMIT