Space qualified GAN Components for Next generation systems

Project Information

SGAN-Next

Grant agreement ID: 101082611

DOI

10.3030/101082611

EC signature date 10 October 2022

Start date 1 December 2022

End date 30 November 2026

Funded under

• Digital, Industry and Space

Total cost

€ 2 889 760,00

EU contribution

€ 2 882 805,75

Coordinated by

SENER TAFS SA
Spain

Periodic Reporting for period 1 - SGAN-Next (Space qualified GAN Components for Next generation systems)

Reporting period: 2022-12-01 to 2025-03-31

Summary of the context and overall objectives of the project

The main objective of SGAN-Next is to develop a fully European GaN on SiC foundry process and demonstrate outstanding performance at high frequency beyond Q-band, through the design of efficient and robust SSPA, LNA and switch devices for flexible LEO/GEO payloads. For this purpose, the project led by SENER as a satellite equipment manufacturer, includes an epitaxy manufacturer (SweGaN), an industrial foundry (UMS), a research foundry (FBH), and two Universities (UNIBO and UAB). Moreover, the consortium count on the two main European satellite prime contractors (ADS and TAS) for the conceptual definition of services and the required system to answer market demand.
SGaN-Next aims to secure a European supply chain with GaN epitaxial wafers provided by SweGaN. For this new process, Q/V band power cells will be designed making use of novel processing modules and epitaxial concepts which reduce parasitic losses and increase thermal drain to the heat sink. In parallel, UMS provides access to its 0.1-µm GaN technology (GH10-10), which will be optimized and submitted to a space qualification assessment through two runs available for MMICs design and validation. Microwave characterization of GaN technology performance by model refinement and device characterization will be addressed to improve the MMIC design process along the project.
As highly efficient PAs are essential for Telecom active antennas with a high number of active units, at least three PAs design concepts are proposed to answer the needs identified at the equipment level. The efficiency has a critical impact on the extra power demanded to the system and the increased complexity to dissipate. On the reception side, a design of an LNA as well as a switch for a robust RF front-end will be addressed. Last, but not least, packaging techniques will be evaluated for space use and finally, a demonstrator of an SSPA for actual antenna systems based on the designed MMIC’s will be developed and tested under space environmental conditions.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

Work Package 2 aims to provide a system-level use case with its requirements and flow-down to demonstrator and MMIC levels. The main objective has been achieved, with the final activity related to evaluation of results continuing until the project's end. System-level requirements for different applications and orbits, such as LEO, MEO, and GEO, have been provided by ADS and TAS.

Work Package 3 focuses on the operations initiated by SweGaN at a new facility with a new MOCVD system, which is expected to increase production capacity significantly. The transfer of normally-on QuanFINE epitaxy to the new MOCVD system has been performed using 4-inch substrates, exhibiting good thickness uniformity, surface morphology, and high electron mobility. SweGaN and UMS have jointly defined the epitaxial specifications for the first learning cycle, with six wafers grown, characterized, and delivered to UMS.

Work Package 4 involves the development of process modules to reduce parasitic elements and improve power cell designs. FBH developed a new technology module for improved ohmic contacts, reducing contact resistance significantly. Additionally, a new technology for gate metallization was developed, allowing for shorter gate metal and increased gate metallization height, which improved device performance.

Work Package 5 focuses on the characterization and evaluation of transistor devices and process modules. Transistor samples from UMS-F and FBH were shipped to UNIBO for S-parameter measurements and passive CW load-pull measurements. The new Q-band active load-pull setup at FBH is under development to feature increased output power levels.

Work Package 6 involves the foundry service in baseline GH10-10 technology and the evaluation of a fully European supply chain for 0.1µm GaN technology. SweGaN epi wafers have been optimized, and the main electrical parameters are close to target and within electrical specifications. The next wafers are planned to be grown and delivered in June 2025.

Work Package 7 involves the design of MMICs for the first foundry run in the project. SENER, UAB, and UNIBO have performed MMIC designs following MMIC requirements. The main MMICs designed for the first run include HPA, LNA, and Switch, with manufacturing by UMS expected to be completed by July 2025.

Work Package 8 focuses on the design of base test fixtures for the measurement of MMICs from the first run. SENER has designed the base test fixtures, which will be assembled in a thermally conductive metallic base using a silver sintering assembly method. The hermetic MHIC is a metallic package with hermetic WG interfaces, and the design is ongoing.

Work Package 9 involves the reliability and robustness assessment of GaN technology. Two test vehicles, Dynamic Evaluation Circuits (DEC) and Representative Integrated Circuit (RIC), will be used for space qualification and radiation tests. The proposed reliability test plan includes process stability endurance tests, radiation hardness assessments, and various reliability campaigns.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

Advancements beyond the state of the art:

Improved Ohmic Contacts: FBH developed a new technology module for improved ohmic contacts, reducing contact resistance from 0.4 Ωmm to 0.14 Ωmm, and on-wafer variation from ±0.14 Ωmm to ±0.02 Ωmm. This led to a decrease in test device on-state resistance from 2.4 Ωmm to 1.9 Ωmm and an increase in 20 GHz RF output power from 4.1 W/mm to 4.5 W/mm.

Electroplated Gate Metallization: A new technology for gate metallization was developed, allowing for shorter gate metal and increased gate metallization height. This reduced gate-metal sheet-resistance from 171 mΩ/sq to 104 mΩ/sq, and increased fmax for devices with 100 nm gate length from 145 GHz to 169 GHz.

Air Gate Tunnel Development: FBH explored a new approach to hermetically encapsulate the transistor’s gate region into a void filled with air, reducing the dielectric permittivity of the gate surrounding. This innovative processing technology is still under development.

These advancements demonstrate significant improvements in contact resistance, gate metallization, and encapsulation techniques, pushing the boundaries of current technology.