Project description DEENESFRITPL Improving efficiency for smart applications From robots to wearables, our society is poised to experience a new wave of smart applications, which will require embedded devices with increased intelligence at a reduced energy and latency cost. However, the slow development cycle of processor chips in comparison to algorithms creates a ‘hardware lottery’, where available hardware platforms determine the selection of algorithms. This innovation deadlock limits efficiency and narrows the market to a few large companies. Funded by the European Research Council, the BINGO project will break this deadlock. It proposes heterogeneous compute platform customisation for a given AI workload in a matter of days through rapid selection and assembly of prefabricated co-processor chiplets. This breakthrough will enable efficient execution of new algorithms. Show the project objective Hide the project objective Objective The next wave of smart applications in our society will need embedded devices (robots, wearables, etc.) with increased intelligence at much reduced energy and latency cost. Compared to current embedded platforms, up to 1000x efficiency gains could be achieved through tight processor-algorithm co-optimization. However, due to the slow development cycle of processor chips (many months to years) in comparison to algorithms (hours to weeks), this co-optimization today merely boils down to selecting algorithms which run well on mature, available hardware. As these processors and their tooling have been optimized for mature algorithms, not the inherently best algorithm “wins”, but the one that happens to best fit the available “old-school” hardware platforms. This “hardware lottery” holds back innovation, severely impacts embedded AI execution efficiency, and narrows the market to a few large companies.The BINGO vision to break this innovation deadlock is to enable heterogeneous compute platform customization for a given AI workload in a matter of days (100x faster), through rapid selection and assembly of prefabricated co-processor chiplets. This needs breakthroughs in: a.) A library of embedded-AI-optimized co-processor chiplets, surpassing the SotA in terms of dataflow heterogeneity for improved efficiency (100x over CPU); and inter-operability in heterogeneous chiplet meshes on a reusable “breadboard” interposer. b.) Rapid cost models and workload schedulers for beyond-SotA heterogeneous platform customization: automatically deriving the optimal chiplet combination for an application, assemble it and deploy, all in a few days.Optimizing across the disciplines of chip design, computer architecture, scheduling, and AI fits perfectly to my expertise gained at KU Leuven, imec and Intel. It will stimulate a surge of embedded AI innovations, enable efficient execution of new algorithms, and bring the EU back at the forefront of chip design and embedded AI research. Fields of science engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringcomputer hardwarecomputer processors Keywords chip(let) design interposer hardware acceleration digital design edge devices machine learning edgeAI tinyML low-power processors heterogeneous multi-core Programme(s) HORIZON.1.1 - European Research Council (ERC) Main Programme Topic(s) ERC-2022-COG - ERC CONSOLIDATOR GRANTS Call for proposal ERC-2022-COG See other projects for this call Funding Scheme ERC - Support for frontier research (ERC) Coordinator KATHOLIEKE UNIVERSITEIT LEUVEN Net EU contribution € 1 995 750,00 Address Oude markt 13 3000 Leuven Belgium See on map Region Vlaams Gewest Prov. Vlaams-Brabant Arr. Leuven Activity type Higher or Secondary Education Establishments Links Contact the organisation Opens in new window Website Opens in new window Participation in EU R&I programmes Opens in new window HORIZON collaboration network Opens in new window Other funding € 0,00
