The BINGO project has completed 30 months (2.5 years) of its five-year duration and is well into its first implementation phase, with significant progress on the core R&D objectives across all five Work Packages (WPs).
In WP1, we developed a unified abstraction framework for AI workloads and hardware accelerator descriptors. This model — now actively used in both our scheduler (Stream) and compiler backend (SNAX-MLIR) — captures memory-compute structures, fusion patterns, and loop dependencies, and has proven essential for hardware-software co-design. WP1 also yielded the SNAX framework, a reusable accelerator shell architecture combining lightweight RISC-V control, tightly coupled memory, and programmable data streamers. SNAX enables modular integration of custom accelerators into shared-memory systems and is now open source, with strong early adoption. The associated DataMaestro abstraction and SNAX-MLIR compiler have enabled rapid co-development across the stack.
In WP2, we developed a suite of specialized AI accelerators aligned with SNAX. Highlights include the OpenGemm matrix engine (ASP-DAC 2025), BitWave (HPCA 2024) for bit-level sparse inference, and the ViT-Edge accelerator (ISCAS 2024) for compact transformer workloads. Three additional unpublished accelerators — targeting compute-in-memory, hyperdimensional computing, and CGRA-based execution — have also been completed and integrated into our flow.
In WP3, the chiplet-to-chiplet communication protocol was finalized, and the digital design of drivers and receivers completed. The interposer technology has been selected. We also acquired bonding infrastructure, completing our lab setup for future chiplet-interposer integration. Building on this, we have defined the near-term integration roadmap: an interposer tape-out is planned for February 2026, followed by the first accelerator chiplet tape-out in May 2026.
In WP4, we developed the Zigzag/Stream scheduling framework (published in IEEE Transactions on Computers), enabling analytical scheduling of layer-fused DNNs on multi-core accelerators. Now open source with over 150 GitHub stars, Stream is used by multiple external groups. It balances memory reuse, inter-core bandwidth, and latency. Additional efforts include COAC (ISQED 2024) and CMDS (VLSI Transactions) for joint hardware and memory-aware scheduling. Compiler development began with TVM (MATCH, TCAD) but transitioned to a more flexible MLIR backend. SNAX-MLIR now supports pipelined asynchronous scheduling and register-level kernel generation.
In WP5, we completed the 2025 tape-out of the multi-accelerator SoC, with 4 AI accelerators and an RV64 (CVA6) RISC-V host core that demonstrates the benefits of heterogeneous compute clusters and validates the end-to-end toolchain from abstraction and compilation to silicon. The SoC is currently being under review for publication.
Together, these results mark a major step toward our overall goal: delivering a functioning, open, and extensible vertical stack to break the hardware lottery in embedded AI design.
