WP1:
Reduction in the cycle time for a 100 V buffer stack by 40% has been achieved, process module updates to improve the CGD/CGS ratio in power transistors and improve the forward gate leakage with lowering the leakage with more than an order of magnitude. Demonstrator lots are being processed using a dedicated ALL2GaN design including power 5 mΩ power transistors and IC designs-on-chip on 200 mm GaN-on-SOI substrates. To leverage the full potential of QuanFINE® GaN on SiC substrates, both D-mode and E-mode HEMTs are being fabricated.
WP2:
200mm high voltage GaN-on-Silicon epitaxy process has been optimized for high volume production and multitool set-up by installing an Advanced Process Control. A GaN-on-Si power stacks have been transferred from a 200 mm production technology to a new 300 mm reactor technology. A stack has been tuned in with bow values well below 50 µm without cracks and sliplines. First electrical buffer data is consistent with stacks grown on 200 mm including the excellent uniformity.
WP3:
The transistor performance is enhanced by process innovation as well as layout improvements. The wafer flow process is optimized in terms of epi growth and HEMT contact and gate module development.
To enable UCs to design their demonstrators a compact model for the active transistors was developed. For accurate modelling, a thorough dynamic characterization of the devices was done. Based on this model, a process design kit (PDK) was provided. To provide a novel integration method, a SMPT-capable technology is developed.
WP4:
The integration of GaN devices will be sought in different levels from bare dies via system-on chip to integrated modules via system-in-module within WP4. Here novel interconnects materials & packaging solutions to minimize parasitic loop-inductances and reduce power consumption & footprint of GaN systems will be investigated.
WP5:
Reliability and robustness test specification for GaN devices has been defined. These tests include power cycling, temperature cycling, vibration and short circuit tests in order to detect failures on interconections, die attach, etc. In the same way, the devices under test have been defined by each partner. First tests have been carried out. In parallel, first device models have been developed. Failure mode mechanisms have been analized.
WP6:
Defining specifications for GaN devices by analyzing application requirements and evaluating use cases through simulation. Developing smart solutions for telecommunication applications, optimizing compact power converters for transport applications, enhancing power converters for data centers, renewable energy, smart grids, and smart cities, and creating a roadmap for future technology development and applications.
