Periodic Reporting for period 1 - ALL2GaN (Affordable smart GaN IC solutions as enabler of greener applications)
Periodo di rendicontazione: 2023-05-01 al 2024-04-30
ALL2GaN will be the backbone for the European Power Electronics Industry by offering an EU-born smart GaN 'Integration Toolbox'. The project will provide the base for applications with significantly increased material- and energy efficiency, thus meeting the global energy needs while keeping the CO2 footprint to the minimum.
The project is a direct response to the European Green Deal challenge and its goals to transform economies to achieve climate neutrality by 2050, without impeding economic growth and by the sustainable use of natural resources. It will directly contribute to energy saving and cutting-edge green technology innovation as well as to a globally competitive and resilient European industry. The 45 project partners from 12 European countries constitute a balanced mix of industry and research with complementary skills and expertise. The multidisciplinary partners cover the entire value chain technology - packaging - reliability - application by striving to achieve eight ambitious objectives:
(1) Push the limits of industrial GaN devices and system-on-chip approaches for ≤100V
(2) Leverage the full potential of innovative substrates for GaN
(3) Achieve novel benchmark solutions for lateral GaN devices and integrated circuits ≥650V
(4) Reach best technical and cost performance of RF GaN on Si with novel integration concepts
(5) Breaking the packaging limits by application driven integrated solutions of high performance GaN products
(6) Advance the methods to evaluate and optimize reliability and robustness of GaN components, modules, and systems for shortest time-to-market and maximum product availability at the end user
(7) Demonstrate highest affordable performance for greener power electronics and RF applications
(8) Road-mapping for the future GaN technology development and applications to support long-term exploitation/business cases and European leadership beyond ALL2GaN
The results of the smart GaN Integration Toolbox will unleash the energy saving and material efficiency potential of GaN. This leads to an average loss reduction of 30% across the Use Cases. After roll-out to all addressable applications, the outcome is a long-term loss reduction of about 86 TWh (EU) which equivalents to about 43 Megatons of CO2 per year and that correlates to 437 TWh (worldwide) which equivalents to about 218 saved Megatons of CO2.
The project is a direct response to the European Green Deal challenge and its goals to transform economies to achieve climate neutrality by 2050, without impeding economic growth and by the sustainable use of natural resources. It will directly contribute to energy saving and cutting-edge green technology innovation as well as to a globally competitive and resilient European industry. The 45 project partners from 12 European countries constitute a balanced mix of industry and research with complementary skills and expertise. The multidisciplinary partners cover the entire value chain technology - packaging - reliability - application by striving to achieve eight ambitious objectives:
(1) Push the limits of industrial GaN devices and system-on-chip approaches for ≤100V
(2) Leverage the full potential of innovative substrates for GaN
(3) Achieve novel benchmark solutions for lateral GaN devices and integrated circuits ≥650V
(4) Reach best technical and cost performance of RF GaN on Si with novel integration concepts
(5) Breaking the packaging limits by application driven integrated solutions of high performance GaN products
(6) Advance the methods to evaluate and optimize reliability and robustness of GaN components, modules, and systems for shortest time-to-market and maximum product availability at the end user
(7) Demonstrate highest affordable performance for greener power electronics and RF applications
(8) Road-mapping for the future GaN technology development and applications to support long-term exploitation/business cases and European leadership beyond ALL2GaN
The results of the smart GaN Integration Toolbox will unleash the energy saving and material efficiency potential of GaN. This leads to an average loss reduction of 30% across the Use Cases. After roll-out to all addressable applications, the outcome is a long-term loss reduction of about 86 TWh (EU) which equivalents to about 43 Megatons of CO2 per year and that correlates to 437 TWh (worldwide) which equivalents to about 218 saved Megatons of CO2.
WP1:
Reduction in the cycle time for a 100 V buffer stack by 40% has been achieved, process module updates to improve the CGD/CGS ratio in power transistors and improve the forward gate leakage with lowering the leakage with more than an order of magnitude. Demonstrator lots are being processed using a dedicated ALL2GaN design including power 5 mΩ power transistors and IC designs-on-chip on 200 mm GaN-on-SOI substrates. To leverage the full potential of QuanFINE® GaN on SiC substrates, both D-mode and E-mode HEMTs are being fabricated.
WP2:
200mm high voltage GaN-on-Silicon epitaxy process has been optimized for high volume production and multitool set-up by installing an Advanced Process Control. A GaN-on-Si power stacks have been transferred from a 200 mm production technology to a new 300 mm reactor technology. A stack has been tuned in with bow values well below 50 µm without cracks and sliplines. First electrical buffer data is consistent with stacks grown on 200 mm including the excellent uniformity.
WP3:
The transistor performance is enhanced by process innovation as well as layout improvements. The wafer flow process is optimized in terms of epi growth and HEMT contact and gate module development.
To enable UCs to design their demonstrators a compact model for the active transistors was developed. For accurate modelling, a thorough dynamic characterization of the devices was done. Based on this model, a process design kit (PDK) was provided. To provide a novel integration method, a SMPT-capable technology is developed.
WP4:
The integration of GaN devices will be sought in different levels from bare dies via system-on chip to integrated modules via system-in-module within WP4. Here novel interconnects materials & packaging solutions to minimize parasitic loop-inductances and reduce power consumption & footprint of GaN systems will be investigated.
WP5:
Reliability and robustness test specification for GaN devices has been defined. These tests include power cycling, temperature cycling, vibration and short circuit tests in order to detect failures on interconections, die attach, etc. In the same way, the devices under test have been defined by each partner. First tests have been carried out. In parallel, first device models have been developed. Failure mode mechanisms have been analized.
WP6:
Defining specifications for GaN devices by analyzing application requirements and evaluating use cases through simulation. Developing smart solutions for telecommunication applications, optimizing compact power converters for transport applications, enhancing power converters for data centers, renewable energy, smart grids, and smart cities, and creating a roadmap for future technology development and applications.
Reduction in the cycle time for a 100 V buffer stack by 40% has been achieved, process module updates to improve the CGD/CGS ratio in power transistors and improve the forward gate leakage with lowering the leakage with more than an order of magnitude. Demonstrator lots are being processed using a dedicated ALL2GaN design including power 5 mΩ power transistors and IC designs-on-chip on 200 mm GaN-on-SOI substrates. To leverage the full potential of QuanFINE® GaN on SiC substrates, both D-mode and E-mode HEMTs are being fabricated.
WP2:
200mm high voltage GaN-on-Silicon epitaxy process has been optimized for high volume production and multitool set-up by installing an Advanced Process Control. A GaN-on-Si power stacks have been transferred from a 200 mm production technology to a new 300 mm reactor technology. A stack has been tuned in with bow values well below 50 µm without cracks and sliplines. First electrical buffer data is consistent with stacks grown on 200 mm including the excellent uniformity.
WP3:
The transistor performance is enhanced by process innovation as well as layout improvements. The wafer flow process is optimized in terms of epi growth and HEMT contact and gate module development.
To enable UCs to design their demonstrators a compact model for the active transistors was developed. For accurate modelling, a thorough dynamic characterization of the devices was done. Based on this model, a process design kit (PDK) was provided. To provide a novel integration method, a SMPT-capable technology is developed.
WP4:
The integration of GaN devices will be sought in different levels from bare dies via system-on chip to integrated modules via system-in-module within WP4. Here novel interconnects materials & packaging solutions to minimize parasitic loop-inductances and reduce power consumption & footprint of GaN systems will be investigated.
WP5:
Reliability and robustness test specification for GaN devices has been defined. These tests include power cycling, temperature cycling, vibration and short circuit tests in order to detect failures on interconections, die attach, etc. In the same way, the devices under test have been defined by each partner. First tests have been carried out. In parallel, first device models have been developed. Failure mode mechanisms have been analized.
WP6:
Defining specifications for GaN devices by analyzing application requirements and evaluating use cases through simulation. Developing smart solutions for telecommunication applications, optimizing compact power converters for transport applications, enhancing power converters for data centers, renewable energy, smart grids, and smart cities, and creating a roadmap for future technology development and applications.
WP1:
Reduction in the cycle time for MOCVD growth of 100 V buffer stacks by 40%.
Lowering of forward gate leakage with more than an order of magnitude in p-GaN lateral HEMTs.
Transfer the QuanFINE® epitaxy process to a new MOCVD system allowing high throughput for substrate fabrication.
WP2:
A GaN-on-Si power stacks have been transferred from a 200 mm production technology to a new 300 mm reactor technology with bow values well below 50 µm, without cracks and sliplines.
1200 V lateral p-GaN gate High Electron Mobility Transistors (HEMTs) using 9 µm-thick buffer stacks on engineered QST® substrates have been fabricated with a hard breakdown voltage of over 2100 V and a Ron of around 29 Ohm-mm at 100 °C.
Integrating in‐chip microfluidic cooling directly on commercially-available GaN power ICs has been demonstrated.
WP3:
Two approaches are used: classical MMIC building and novel SMPT. Core of both approaches is the RFGAN-SI technology that is developed according to the requirements defined for use cases covering a wide range of power levels and frequency ranges. The intrinsic transistor performance aims to fulfill a set of key performance indicators (KPIs) that contain a gain target, an efficiency target, a bandwidth indicator, and a loss indicator.
WP4:
Micro-Fabrication of unprecedented packaging processes and materials for GaN assembly and integration.
Design & conceptualization of fine-pitch flipchip interconnect schemes (20-50 µm pitch size) for SMPT GaN micro-assembly in the 1st year.
System-in-module concept for GaN-based PV inverter applications in the 12 kW class.
WP5:
Overview of GaN specific failure modes and mechanisms including associated parameters.
First automated workflow for ECCI measurement and analysis available, feasibility for active devices planned.
WP6:
Connectivity: 6 Conceptual demonstrator PAs designed (UC1B, UC1C1, UC1C2 using RF-GaN-FX) Power KPIs met, Efficiency KPIs mostly met.
Transport: Expecting a 30% lower volume in the EV charger, due to lower cooling requirements and lower losses power stage.
Energy: In terms of efficiency Server power supply is on good track. Testing the possible 20mΩ Gan transistor with driver the LLC converter.
Reduction in the cycle time for MOCVD growth of 100 V buffer stacks by 40%.
Lowering of forward gate leakage with more than an order of magnitude in p-GaN lateral HEMTs.
Transfer the QuanFINE® epitaxy process to a new MOCVD system allowing high throughput for substrate fabrication.
WP2:
A GaN-on-Si power stacks have been transferred from a 200 mm production technology to a new 300 mm reactor technology with bow values well below 50 µm, without cracks and sliplines.
1200 V lateral p-GaN gate High Electron Mobility Transistors (HEMTs) using 9 µm-thick buffer stacks on engineered QST® substrates have been fabricated with a hard breakdown voltage of over 2100 V and a Ron of around 29 Ohm-mm at 100 °C.
Integrating in‐chip microfluidic cooling directly on commercially-available GaN power ICs has been demonstrated.
WP3:
Two approaches are used: classical MMIC building and novel SMPT. Core of both approaches is the RFGAN-SI technology that is developed according to the requirements defined for use cases covering a wide range of power levels and frequency ranges. The intrinsic transistor performance aims to fulfill a set of key performance indicators (KPIs) that contain a gain target, an efficiency target, a bandwidth indicator, and a loss indicator.
WP4:
Micro-Fabrication of unprecedented packaging processes and materials for GaN assembly and integration.
Design & conceptualization of fine-pitch flipchip interconnect schemes (20-50 µm pitch size) for SMPT GaN micro-assembly in the 1st year.
System-in-module concept for GaN-based PV inverter applications in the 12 kW class.
WP5:
Overview of GaN specific failure modes and mechanisms including associated parameters.
First automated workflow for ECCI measurement and analysis available, feasibility for active devices planned.
WP6:
Connectivity: 6 Conceptual demonstrator PAs designed (UC1B, UC1C1, UC1C2 using RF-GaN-FX) Power KPIs met, Efficiency KPIs mostly met.
Transport: Expecting a 30% lower volume in the EV charger, due to lower cooling requirements and lower losses power stage.
Energy: In terms of efficiency Server power supply is on good track. Testing the possible 20mΩ Gan transistor with driver the LLC converter.