14 Angstroms Module Integration

Project Information

14AMI

Grant agreement ID: 101111948

DOI

10.3030/101111948

EC signature date 10 May 2023

Start date 1 May 2023

End date 31 October 2026

Funded under

• Digital, Industry and Space

Total cost

€ 108 927 481,90

EU contribution

€ 24 954 145,00

Coordinated by

ASML NETHERLANDS B.V.
Netherlands

Periodic Reporting for period 2 - 14AMI (14 Angstroms Module Integration)

Reporting period: 2024-05-01 to 2025-04-30

Summary of the context and overall objectives of the project

In the context of Moore’s law, the 14AMI project enables the microelectronics industry to migrate to the next technology node. The overall objective of the project is to explore and realize solutions for the manufacture of 14 Angstrom CMOS chip technology, addressing: Lithography, Metrology, and Process technology.
The 14AMI project will support the partners and their supplier network to stay at the leading edge of high-tech developments, crucial to meet the digitization challenges of the European society. Technological excellence and the ability of talent to move freely within Europe will allow for state-of-the art innovation to flourish.
Scientific: 14AMI will demonstrate a cost efficient solution for 14A technology node, shifting the technological boundaries and understanding of new 14A technology nodes, including lithography, 3D metrology, characterization, and design and process technology
Economic: 14AMI will “boost industrial competitiveness” in the EU, stimulating job growth in a broad ecosystem consisting of large industrial and SME, OEMs, joint development partners and suppliers as well as knowledge institutes to continue the developments of new processes and modules for advanced nodes technologies. 14AMI will generate new partnerships, businesses and create new jobs, and attract talents in Europe.
Societal: Enabling new application in areas such as security, communication and enabling of further automation in mobility, health and research. With respect to sustainability, 14AMI will develop of more sustainable material and processing alternatives in addition to a reduced carbon footprint of the EUV-chips.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

Lithography
Significant advances have been made to understand the interaction of EUV plasma with the optics surfaces within the ASML scanner:
- Activities on increasing the source power through increasing the frequency of Tin droplets were successful on an offline set-up and will now be pursued further (Figure 1).
- A digital twin for the source droplet generator is included in the 14AMI project and is a powerful tool for predicting the module behaviour.
- As the EXE machine requires image stitching, a wafer stocker has been pursued and is shown to be a major development which will cut scanner overhead and lead to productivity gains for the foundries (Figure 2)

Holistic Metrology and Quality Control
Progress has been made in advancing metrology and process control:
Regarding wafer-based metrology and process control platforms, a test bench of wavefront reconstruction for the next generation wafer inspection tool is developed. Dense sampling for high-order corrections is developed, boosting throughput. Integration of a new XRR analysis engine is completed that is compatible for both scanning and static tools. A series of tests focused on optimizing both Ga and Ar ion beam polishing processes is continued.
A first prototype of the modular e-beam column is nearing completion. An improved edge symmetry imaging for an array of contact holes is demonstrated. The test and validation rig for the 4D-STEM detector has been realized. Lamellae were extracted and set on Si substrates and analyzed.
Probe based technologies included developing, prototyping and testing new high aspect ratio SPM probes and measured Mid-Aspect Ratio line space, having the critical dimension below 10nm with newly developed 8nm probes.
Chemical measurement systems have been produced first photomask stripping results and IMINA for electrical probers.
Novel reconstruction algorithms and high-resolution thermo-optical imaging systems were developed, focusing on damage detection and optical readout.
A stand-alone prototype Aerial Image Simulator for EUV illumination is developed. Good agreement between the virtual AIMS simulations and real AIMS images are achieved. EUV mask degradation is evaluated and plasma characterization tests were performed. Mask features thickness and sidewall angle are analysed.
CD maps and CD variations were compared, and shown to be well correlated. Overlay mark development demonstrated feasibility of minimizing the target-to-device bias.
Convolutional Neural Networks defect classification, SEM measurement automation, and ML-based techniques for die-to-die extrapolation were explored. New methodologies for Cu plating and particle detection down to 200nm were validated.
See also Figure 3 and Figure 4 attached.

CFET Modules Integration and Sustainable Process Technology
Major advancements were achieved in CFET module integration and sustainable process development:
CMOS CFET integration: Front-end module development progressed through to replacement metal gate integration (Figure 5). Two-level frontside MOL integration for connecting top and bottom devices in CFET architecture also advanced significantly (Figure 6).
Sequential CFET: Nanosheet stacks with embedded middle dielectric isolation (EMDI) and hybrid channels were successfully manufactured. Laser release modules were upgraded to meet industry throughput standards.
Wafer sorter development: The next-generation wafer sorter with integrated dual-head inspection has completed design; prototype build is underway and expected to finish by summer.
PFAS-free lithography: First-generation PFAS-free ArF dry resists were evaluated, showing comparable sensitivity and resolution, with further optimization needed for process window enhancement.
Smart sensor technology: A novel unsupervised anomaly detection method for spectral data was developed to monitor process chamber stability.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

Work is ongoing, and final results demonstrating advancements beyond the state of the art will be reported at the end of the project. However, significant progress has already been made in several key areas:
Processes for monolithic CMOS CFET devices, comprising supper lattice growth for CFET stacks, etch/metallization solutions for (extreme) high aspect features such as gate patterning, contact patterning/ metallization. Solutions for integration of front-side double contacts. New hardware and process solutions for manufacturing sequential CFET with embedded middle dielectric isolation and hybrid channels. Sorter with integrated two-sided inspection metrology-unit. PFAS-free resist technology for ArF dry lithography. Smart sensor technology/software for anomaly detection in process chambers.

Short loop CFET device wafer

Operating principle of an LPP EUV source

Reinforcement learning

CMOS CFET module development

Overhead due to mask exchange

Imina and CSEM automatic alignment