Periodic Reporting for period 1 - 14AMI (14 Angstroms Module Integration)
Período documentado: 2023-05-01 hasta 2024-04-30
In the context of Moore’s law, the 14AMI project enables the microelectronics industry to migrate to the next technology node. The overall objective of the project is to explore and realize solutions for the manufacture of 14 Angstrom CMOS chip technology, addressing: Lithography, Metrology, and Process technology. The 14AMI project will support the partners and their supplier network to stay at the leading edge of high-tech developments, crucial to meet the digitization challenges of the European society. Technological excellence and the ability of talent to move freely within Europe will allow for state-of-the art innovation to flourish.
Scientific: 14AMI will demonstrate a cost efficient solution for 14A technology node, shifting the technological boundaries and understanding of new 14A technology nodes, including lithography, 3D metrology, characterization, and design and process technology
Economic: 14AMI will “boost industrial competitiveness” in the EU, stimulating job growth in a broad ecosystem consisting of large industrial and SME, OEMs, joint development partners and suppliers as well as knowledge institutes to continue the developments of new processes and modules for advanced nodes technologies. 14AMI will generate new partnerships, businesses and create new jobs, and attract talents in Europe.
Societal: Enabling new application in areas such as security, communication and enabling of further automation in mobility, health and research.
Sustainability: 14AMI will develop of more sustainable material and processing alternatives in addition to a reduced carbon footprint of the EUV-chips.
Scientific: 14AMI will demonstrate a cost efficient solution for 14A technology node, shifting the technological boundaries and understanding of new 14A technology nodes, including lithography, 3D metrology, characterization, and design and process technology
Economic: 14AMI will “boost industrial competitiveness” in the EU, stimulating job growth in a broad ecosystem consisting of large industrial and SME, OEMs, joint development partners and suppliers as well as knowledge institutes to continue the developments of new processes and modules for advanced nodes technologies. 14AMI will generate new partnerships, businesses and create new jobs, and attract talents in Europe.
Societal: Enabling new application in areas such as security, communication and enabling of further automation in mobility, health and research.
Sustainability: 14AMI will develop of more sustainable material and processing alternatives in addition to a reduced carbon footprint of the EUV-chips.
Lithography
For developing a scanner and an upgrade package to manufacture the 14A node, the focus on the first period of the project was on adaptive EUV mirrors, optics lifetime, productivity improvements by increasing scanner tool source power, yield improvements by reducing contamination and better overlay. Significant progress has been made in all areas, on target for the final goal at the end of the project.
Holistic Metrology and Quality Control
Wafer-based: AMIL, OKO included the definition of wavefront reconstruction specifications and data collection from the brightfield inspection tool at AMIL and formalized the problem of finding an optimal actuator geometry by OKO. KLA develops new algorithms which remove dependence of measured overlay on the choice of target area before the measurement algorithm is applied. BRT develops new XRR/HRXRD analysis software. BRT and ANCOSYS studied the effects of the chemical bath on the bonding quality at the advanced packaging side of the semiconductor process. To prepare a reference metrology, UPB experiments with the extraction of lamellas from samples and analyses them using TEM for setting the initial parameters.
AMIL, ICT and CSEM develop better E-beam contrast and symmetry for EUV HNA resist samples with improved computing performance. THERMO completed the design and scope definition for integration of sub-nm crystallographic information analysis with dimensional and compositional analysis in TEM solutions. UPB investigated hybrid metrology methods based on combined SPM and e-beam. NFI develops and tests new high aspect ration SPM probes. ANCOSYS chemical measurement systems have been set up to monitor photomask stripping and IMINA for electrical probers developed from the technical specifications to a working prototype, a new compact piezo actuated nano positioning XYZ stage with position sensors. TNO AFM activity included the implementation of two reconstruction algorithms: Intermodulation AFM and inverting dynamic AFM. In addition, TNO started the development of HEROISM.
Mask-based: Zeiss accelerates mask repair cycles through direct aerial image simulations of SEM images. Fraunhofer IISB complement Zeiss activity with model development for the virtual AIMS simulation and started development of a three-dimensional mask model to represent real mask structures from SEM images. TNO explored EUV mask degradation with modeling and feasibility study on different biasing approaches to tailor the ion energy distribution in the plasma and selected a setup to perform the tests. UPB started with mask features thickness and sidewall angle analysis. AMIL developed and performed on DUV mask a Massive CD measurements of the line/space structures across the entire area of the mask for both repetitive and non-repetitive patterns. KLA started with overlay design guidance to minimize litho and process effects on OVL mark.
Holistic: TUD investigates the applicability of ML, online learning, and data fusion in combination with active input approach, based on the data provided by partners (NOVA, BRT and AMIL). CSEM and IMINA gather specification to leverage AI to process scanning electron microscope images to help the operator locate defects on a chip and move electrical nanoprobes to them. NOVA defined the holistic hybridisation SW framework and algorithms. ANCO and BRT established electrochemical monitoring for Cu plating baths in Cu TSV plating process. Fastmicro has made a concept design of a compact automated fast wafer scanner based on an equipment front-end module (EFEM).
CFET Modules Integration and Sustainable Process Technology
For 'CFET Modules Integration', major progress was made. For the manufacturing of CMOS CFET devices, related to the front-end-of-line (FEOL), the processes for nanosheet stack growth/patterning, dummy gate, gate spacer, middle dielectric isolation, source/drain recess, inner spacer and source/drain modules are now available (Figure 1). Also the work related to the integration of a double/2-level frontside middle-of-line (MOL), to connect respectively the bottom and top device in a CFET architecture, has started. Proof of concept was demonstrated using short loop integration vehicles (Figure 2). For sequential CFET integration, process development focused on wafer bonding using next generation hardware, i.e. laser module for layer release, plasma module for surface activation. Also, the product design for next generation wafer sorter with integrated inspection module has been completed.
For 'Sustainable Technology Solution', first generation of PFAS-lite photo resists, for 193i lithography, have been synthesized. The litho performance was demonstrated to be equivalent to the state of the art resists. The imec.netzero software has been extended to also quantify the ecological impact of mask manufacturing in chips manufacturing. Sensor prototypes, for anomaly detection in semiconductor hardware, have been developed.
For developing a scanner and an upgrade package to manufacture the 14A node, the focus on the first period of the project was on adaptive EUV mirrors, optics lifetime, productivity improvements by increasing scanner tool source power, yield improvements by reducing contamination and better overlay. Significant progress has been made in all areas, on target for the final goal at the end of the project.
Holistic Metrology and Quality Control
Wafer-based: AMIL, OKO included the definition of wavefront reconstruction specifications and data collection from the brightfield inspection tool at AMIL and formalized the problem of finding an optimal actuator geometry by OKO. KLA develops new algorithms which remove dependence of measured overlay on the choice of target area before the measurement algorithm is applied. BRT develops new XRR/HRXRD analysis software. BRT and ANCOSYS studied the effects of the chemical bath on the bonding quality at the advanced packaging side of the semiconductor process. To prepare a reference metrology, UPB experiments with the extraction of lamellas from samples and analyses them using TEM for setting the initial parameters.
AMIL, ICT and CSEM develop better E-beam contrast and symmetry for EUV HNA resist samples with improved computing performance. THERMO completed the design and scope definition for integration of sub-nm crystallographic information analysis with dimensional and compositional analysis in TEM solutions. UPB investigated hybrid metrology methods based on combined SPM and e-beam. NFI develops and tests new high aspect ration SPM probes. ANCOSYS chemical measurement systems have been set up to monitor photomask stripping and IMINA for electrical probers developed from the technical specifications to a working prototype, a new compact piezo actuated nano positioning XYZ stage with position sensors. TNO AFM activity included the implementation of two reconstruction algorithms: Intermodulation AFM and inverting dynamic AFM. In addition, TNO started the development of HEROISM.
Mask-based: Zeiss accelerates mask repair cycles through direct aerial image simulations of SEM images. Fraunhofer IISB complement Zeiss activity with model development for the virtual AIMS simulation and started development of a three-dimensional mask model to represent real mask structures from SEM images. TNO explored EUV mask degradation with modeling and feasibility study on different biasing approaches to tailor the ion energy distribution in the plasma and selected a setup to perform the tests. UPB started with mask features thickness and sidewall angle analysis. AMIL developed and performed on DUV mask a Massive CD measurements of the line/space structures across the entire area of the mask for both repetitive and non-repetitive patterns. KLA started with overlay design guidance to minimize litho and process effects on OVL mark.
Holistic: TUD investigates the applicability of ML, online learning, and data fusion in combination with active input approach, based on the data provided by partners (NOVA, BRT and AMIL). CSEM and IMINA gather specification to leverage AI to process scanning electron microscope images to help the operator locate defects on a chip and move electrical nanoprobes to them. NOVA defined the holistic hybridisation SW framework and algorithms. ANCO and BRT established electrochemical monitoring for Cu plating baths in Cu TSV plating process. Fastmicro has made a concept design of a compact automated fast wafer scanner based on an equipment front-end module (EFEM).
CFET Modules Integration and Sustainable Process Technology
For 'CFET Modules Integration', major progress was made. For the manufacturing of CMOS CFET devices, related to the front-end-of-line (FEOL), the processes for nanosheet stack growth/patterning, dummy gate, gate spacer, middle dielectric isolation, source/drain recess, inner spacer and source/drain modules are now available (Figure 1). Also the work related to the integration of a double/2-level frontside middle-of-line (MOL), to connect respectively the bottom and top device in a CFET architecture, has started. Proof of concept was demonstrated using short loop integration vehicles (Figure 2). For sequential CFET integration, process development focused on wafer bonding using next generation hardware, i.e. laser module for layer release, plasma module for surface activation. Also, the product design for next generation wafer sorter with integrated inspection module has been completed.
For 'Sustainable Technology Solution', first generation of PFAS-lite photo resists, for 193i lithography, have been synthesized. The litho performance was demonstrated to be equivalent to the state of the art resists. The imec.netzero software has been extended to also quantify the ecological impact of mask manufacturing in chips manufacturing. Sensor prototypes, for anomaly detection in semiconductor hardware, have been developed.
During this period, the lithography scanner specifications for the 14A node have been set, see Figure 3. The foundations have been laid to achieve the overlay specification, as shown below, but also throughput, yield and optics lifetime.
Processes for manufacturing of monolithic integrated CMOS CFET devices, comprising supper lattice growth for CFET stacks, etch/metallization solutions for (extreme) high aspect features such as gate patterning, contact patterning and metallization. Integration of middle dielectric isolation for bottom- and top-device isolation. Solutions for integration of front-side double middle of line. New hardware for sequential CFET with embedded middle dielectric isolation. PFAS-lean resist technology for 193i lithography.
Processes for manufacturing of monolithic integrated CMOS CFET devices, comprising supper lattice growth for CFET stacks, etch/metallization solutions for (extreme) high aspect features such as gate patterning, contact patterning and metallization. Integration of middle dielectric isolation for bottom- and top-device isolation. Solutions for integration of front-side double middle of line. New hardware for sequential CFET with embedded middle dielectric isolation. PFAS-lean resist technology for 193i lithography.