Periodic Reporting for period 1 - 10ACe (10 Angstrom CMOS exploration)
Período documentado: 2024-05-01 hasta 2025-04-30
The objective of the 10ÅCe project is to explore and realize solutions for the 10Å CMOS chip technology. Its
consortium covers the entire value chain for manufacture of 10 Å node CMOS chips, that is, from chip design to
lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing
technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node
and progress Moore’s law to the next node.
The 10ÅCe project is structured on the following four pillars.
Lithography Equipment: ASML and expert EUV partners ZEISS DE, FastMicro, IOM, Plasma Matters, TNO,
TU/e, University of Twente and VDL-ETG will:
• Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield.
• Increase sustainability of the EUV tool, both during production as well as increasing the times a module
in an EUV tool can be refurbished.
Chip design and mask optimization: Imec with the involvement of expert imaging, CAD and IP design partners
ARM, ASML and Siemens will:
• Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and
area.
• Development of new computational lithography solutions to print 10Å CFET structures, to improve
imaging by next generation mask design.
Process Technology: As the ultimate device for logic, the CFET architecture is proposed. Imec and expert partners
Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, ZEISS IL and Wooptix will:
• Demonstrate a fully functional monolithic CFET (mCFET)
• Increase sustainability of the chip manufacturing process, across the manufacturing flow and including
resist material development.
Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will:
• Explore and realize high wafer throughput and sample density, for analysis and characterization of 10Å
3D CFET devices, interconnect and materials I
consortium covers the entire value chain for manufacture of 10 Å node CMOS chips, that is, from chip design to
lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing
technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node
and progress Moore’s law to the next node.
The 10ÅCe project is structured on the following four pillars.
Lithography Equipment: ASML and expert EUV partners ZEISS DE, FastMicro, IOM, Plasma Matters, TNO,
TU/e, University of Twente and VDL-ETG will:
• Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield.
• Increase sustainability of the EUV tool, both during production as well as increasing the times a module
in an EUV tool can be refurbished.
Chip design and mask optimization: Imec with the involvement of expert imaging, CAD and IP design partners
ARM, ASML and Siemens will:
• Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and
area.
• Development of new computational lithography solutions to print 10Å CFET structures, to improve
imaging by next generation mask design.
Process Technology: As the ultimate device for logic, the CFET architecture is proposed. Imec and expert partners
Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, ZEISS IL and Wooptix will:
• Demonstrate a fully functional monolithic CFET (mCFET)
• Increase sustainability of the chip manufacturing process, across the manufacturing flow and including
resist material development.
Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will:
• Explore and realize high wafer throughput and sample density, for analysis and characterization of 10Å
3D CFET devices, interconnect and materials I
Lithography equipment
During the first year, efforts to improve the performance and defectivity of the lithography scanner focused on developing and refining test setups and prototypes intended for validating new technologies. Simulation models were also created to support the fitting of experimental data.
For instance, in the Particle Release Setup, a beam shutter was engineered to shield the release wafer from electron exposure during the ignition and stabilization phases of the electron beam (see Figure 1).
The sustainability dimension was actively addressed as well. Work to date has involved screening approximately 38,000 materials for the presence of PFAS. Two optimal analytical tools for PFAS detection and screening were identified and selected. Partners have since initiated detailed substitution screening and begun testing alternative materials.
Chip design and mask optimisation
Notable advancements in the development of sophisticated mask design and optimization strategies for 0.55 NA EUV lithography. Among the key outcomes was the successful validation of a Design Technology Co-Optimization (DTCO) methodology for CFET benchmarking using a virtual fabrication environment. The team also delivered a functional mini standard cell library characterized with parasitic-aware modeling. Early insights were gained into block-level challenges and opportunities associated with CFET implementation. In addition, progress was made in advanced mask design and Optical Proximity Correction (OPC) modeling tailored for 0.55 NA EUV, alongside the development of automation tools to streamline OPC and model reporting process
Process Technology
For 10A node devices, process development progressed to source/drain integration for the top nanosheet in monolithic CFETs (Figure 2), with replacement metal contacts introduced to address contamination and thermal constraints. Backside contact integration reached a first proof-of-concept (Figure 3), supported by next-gen wafer bonding and metrology tools. In BEOL, variable line width interconnects were demonstrated down to 18 nm pitch and aspect ratios up to 6, with partial airgap isolation reducing capacitance. PFAS-free photoresists were also developed, matching the performance of PFAS-based alternatives.
Process Characterisation
Recent developments in advanced metrology and inspection technologies include prototype implementations for simultaneous quantitative EELS and EDX chemical element analysis. Progress has also been made in machine learning-based TEM metrology, particularly in enhancing user interfaces for automated routines. Early work has begun on a methodology to assess “fleet readiness” across diverse TEM and XDB systems commonly used in semiconductor manufacturing. In parallel, efforts are underway to generate synthetic SEM images using machine learning, including CAD-to-SEM image creation with noise, pattern variation, and defect implantation. Throughput improvements in OCD metrology are being pursued by fitting dual measuring units into a single tool footprint, while overlay measurement accuracy is being enhanced via wafer stage upgrades. For X-ray metrology, workflow optimizations and hardware upgrades—such as faster detectors and improved alignment processes—are being implemented to double alignment speed and boost read-out rates.
During the first year, efforts to improve the performance and defectivity of the lithography scanner focused on developing and refining test setups and prototypes intended for validating new technologies. Simulation models were also created to support the fitting of experimental data.
For instance, in the Particle Release Setup, a beam shutter was engineered to shield the release wafer from electron exposure during the ignition and stabilization phases of the electron beam (see Figure 1).
The sustainability dimension was actively addressed as well. Work to date has involved screening approximately 38,000 materials for the presence of PFAS. Two optimal analytical tools for PFAS detection and screening were identified and selected. Partners have since initiated detailed substitution screening and begun testing alternative materials.
Chip design and mask optimisation
Notable advancements in the development of sophisticated mask design and optimization strategies for 0.55 NA EUV lithography. Among the key outcomes was the successful validation of a Design Technology Co-Optimization (DTCO) methodology for CFET benchmarking using a virtual fabrication environment. The team also delivered a functional mini standard cell library characterized with parasitic-aware modeling. Early insights were gained into block-level challenges and opportunities associated with CFET implementation. In addition, progress was made in advanced mask design and Optical Proximity Correction (OPC) modeling tailored for 0.55 NA EUV, alongside the development of automation tools to streamline OPC and model reporting process
Process Technology
For 10A node devices, process development progressed to source/drain integration for the top nanosheet in monolithic CFETs (Figure 2), with replacement metal contacts introduced to address contamination and thermal constraints. Backside contact integration reached a first proof-of-concept (Figure 3), supported by next-gen wafer bonding and metrology tools. In BEOL, variable line width interconnects were demonstrated down to 18 nm pitch and aspect ratios up to 6, with partial airgap isolation reducing capacitance. PFAS-free photoresists were also developed, matching the performance of PFAS-based alternatives.
Process Characterisation
Recent developments in advanced metrology and inspection technologies include prototype implementations for simultaneous quantitative EELS and EDX chemical element analysis. Progress has also been made in machine learning-based TEM metrology, particularly in enhancing user interfaces for automated routines. Early work has begun on a methodology to assess “fleet readiness” across diverse TEM and XDB systems commonly used in semiconductor manufacturing. In parallel, efforts are underway to generate synthetic SEM images using machine learning, including CAD-to-SEM image creation with noise, pattern variation, and defect implantation. Throughput improvements in OCD metrology are being pursued by fitting dual measuring units into a single tool footprint, while overlay measurement accuracy is being enhanced via wafer stage upgrades. For X-ray metrology, workflow optimizations and hardware upgrades—such as faster detectors and improved alignment processes—are being implemented to double alignment speed and boost read-out rates.
In year 1 the consortium is gearing up to the beyond the state of the art results which are planned in the next years