Periodic Reporting for period 2 - SUPERCHIP (Scalable Unified Processor Enhancing Revolutionary Computing, Harnessing Integrated Performance for Edge AI, Autonomous Driving, Generative AI, and Decentralized AIoT Applications)
Berichtszeitraum: 2024-07-01 bis 2025-06-30
VSORA’s project addresses a critical gap in AI hardware by introducing a novel processor architecture that combines energy efficiency, high performance, and programmability. AI is transforming society but poses major technological and environmental challenges, especially in energy-hungry applications like autonomous vehicles and data centers. Current platforms are fragmented, inefficient, and fail to meet the performance and power demands of full autonomy or large-scale AI inference.
VSORA’s solution is a single-die architecture used in two processor families: TYR, for edge AI in autonomous vehicles, and JOTUNN, for scalable datacenter inference. TYR chips process data from dozens of sensors with ultra-low latency and minimal power, thanks to a shared high-bandwidth memory system and independent AI/DSP execution. JOTUNN uses the same design principles—optimized for hyperscale deployments—to maximize throughput and energy efficiency for modern AI workloads.
Validated with major industrial partners, the architecture meets seven interdependent constraints (power, latency, scalability, programmability, etc.) that no existing solution addresses holistically. Fabricated with advanced 5nm technology and CoWoS packaging, these chips are ready for integration into next-generation automotive and cloud systems.
Beyond performance, the project supports Europe’s digital sovereignty, sustainability goals, and ethical AI deployment—aligning with the European Green Deal and Chips Act. It also opens the door for future engagement with social sciences to address AI’s societal impact.
In short, TYR and JOTUNN enable sustainable, sovereign AI infrastructure—developed in Europe—for both edge and cloud.
VSORA’s solution is a single-die architecture used in two processor families: TYR, for edge AI in autonomous vehicles, and JOTUNN, for scalable datacenter inference. TYR chips process data from dozens of sensors with ultra-low latency and minimal power, thanks to a shared high-bandwidth memory system and independent AI/DSP execution. JOTUNN uses the same design principles—optimized for hyperscale deployments—to maximize throughput and energy efficiency for modern AI workloads.
Validated with major industrial partners, the architecture meets seven interdependent constraints (power, latency, scalability, programmability, etc.) that no existing solution addresses holistically. Fabricated with advanced 5nm technology and CoWoS packaging, these chips are ready for integration into next-generation automotive and cloud systems.
Beyond performance, the project supports Europe’s digital sovereignty, sustainability goals, and ethical AI deployment—aligning with the European Green Deal and Chips Act. It also opens the door for future engagement with social sciences to address AI’s societal impact.
In short, TYR and JOTUNN enable sustainable, sovereign AI infrastructure—developed in Europe—for both edge and cloud.
Manufacturing a new processor is highly complex and time-consuming. VSORA has successfully validated its novel architecture using simulation models—SystemC-TLM and RTL—ensuring it mirrors the final chip’s behavior at the register level.
The final chip configuration has been defined, including the number of compute units and internal memory. Key IP blocks from suppliers were selected after thorough technical and commercial evaluations, integrated into the design, and behavioral models were created to support software development, such as drivers for chip booting.
We have now completed the place & route stage, involving dozens of engineers, and integrated essential test components (BIST, ATPG). RTL code is frozen, and final validations are underway before tape-out. In parallel, we designed the chip package, which integrates multiple dies and HBM memory using CoWoS technology—requiring joint simulation with the chip to model power delivery and voltage drops accurately.
On the software side, we advanced the compiler stack, including binary generation and neural network graph compilation, and expanded our test base, executed on an emulation platform.
VSORA has also played an active role in industry dissemination—engaging with the Automotive Chiplet Association (IMEC), hosting forums in Cambridge and Munich, and participating in major European events such as CARNET Ecosystem Day, Hello Tomorrow, and the AI Continent Action Plan Roundtable. These efforts helped validate use cases, collect feedback, and align the project with European priorities in AI, semiconductors, and digital sovereignty.
The final chip configuration has been defined, including the number of compute units and internal memory. Key IP blocks from suppliers were selected after thorough technical and commercial evaluations, integrated into the design, and behavioral models were created to support software development, such as drivers for chip booting.
We have now completed the place & route stage, involving dozens of engineers, and integrated essential test components (BIST, ATPG). RTL code is frozen, and final validations are underway before tape-out. In parallel, we designed the chip package, which integrates multiple dies and HBM memory using CoWoS technology—requiring joint simulation with the chip to model power delivery and voltage drops accurately.
On the software side, we advanced the compiler stack, including binary generation and neural network graph compilation, and expanded our test base, executed on an emulation platform.
VSORA has also played an active role in industry dissemination—engaging with the Automotive Chiplet Association (IMEC), hosting forums in Cambridge and Munich, and participating in major European events such as CARNET Ecosystem Day, Hello Tomorrow, and the AI Continent Action Plan Roundtable. These efforts helped validate use cases, collect feedback, and align the project with European priorities in AI, semiconductors, and digital sovereignty.
Securing funding is crucial for semiconductor projects, as they are high-risk, high-reward investments. The EIC grant is essential for de-risking key bottlenecks and signaling the potential of our advanced chip solution to European investors.
With the EIC €2.5M grant, we reached TRL8, completing chip design, packaging, and prototyping. The upcoming EIC equity investment will help us achieve TRL9, finalize our Series B round (€40M), and secure global customers. This funding is critical to gaining market leadership and revitalizing the EU semiconductor industry.
The SUPERCHIP project has resulted in an advanced AI inference processor with integrated DSP capabilities, built using cutting-edge 5nm technology. The design is complete, and we’ve secured HBM memory supply. A full software toolchain, including custom compilers and embedded libraries, has been developed for deployment.
The processor meets ISO 26262 standards for automotive safety, making it suitable for ADAS and autonomous driving. Full certification is needed for broader automotive adoption. Simultaneously, we’ve started commercializing the product, attending industry events, and establishing partnerships.
Next steps include integration into datacenter environments, scaling production, and expanding globally, especially in the US and Asia. Additional funding is needed to support these efforts and ensure successful adoption of this European innovation in AI and HPC markets.
With the EIC €2.5M grant, we reached TRL8, completing chip design, packaging, and prototyping. The upcoming EIC equity investment will help us achieve TRL9, finalize our Series B round (€40M), and secure global customers. This funding is critical to gaining market leadership and revitalizing the EU semiconductor industry.
The SUPERCHIP project has resulted in an advanced AI inference processor with integrated DSP capabilities, built using cutting-edge 5nm technology. The design is complete, and we’ve secured HBM memory supply. A full software toolchain, including custom compilers and embedded libraries, has been developed for deployment.
The processor meets ISO 26262 standards for automotive safety, making it suitable for ADAS and autonomous driving. Full certification is needed for broader automotive adoption. Simultaneously, we’ve started commercializing the product, attending industry events, and establishing partnerships.
Next steps include integration into datacenter environments, scaling production, and expanding globally, especially in the US and Asia. Additional funding is needed to support these efforts and ensure successful adoption of this European innovation in AI and HPC markets.