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Energy-Efficient Highly Accurate Data Prefetching

Project description

A hardware design for the Berti data prefetcher

Data prefetchers are crucial for high-performance computers, as they can hide long-latency memory accesses, thereby enhancing speed and efficiency. Despite their significant performance benefits, there has been limited effort to improve their energy efficiency, which is influenced by their accuracy. The ERC-funded Berti-Chip project aims to develop a hardware design for the promising Berti data prefetcher, which offers high performance and accuracy while minimising energy overhead and ensuring cost-effectiveness. The project intends to leverage this efficiency, predicting that it could become essential in the expanding low-power edge market and for high-performance computers.

Objective

Data prefetchers are ubiquitous in current high-performance computers such as those manufactured by Intel, ARM, AMD, or IBM, as they play a fundamental role in hiding long-latency memory accesses. Prefetchers predict the data that will be needed by a processor in the future and fetch such data ahead of execution. State-of-the-art data prefetchers, push the limits of performance but often without caring about energy efficiency. The energy efficiency of a prefetcher is dictated by its accuracy, which measures the percentage of data moved by the prefetcher that satisfies the processor demands.

Berti is a data prefetcher sited at the first-level data cache (L1D) that makes a compelling case for timeliness and accuracy. Berti can boost processors performance by 33% (with respect to those not using prefetching mechanisms) and 8.5% (when compared to mainstream prefetchers) while providing an accuracy above 90%, which translates into a low energy overhead of the memory hierarchy. In addition, Berti is a cost-effective prefetcher that just requires 2.55KB of storage.

The objective of this project is to elaborate a hardware design for the Berti data prefetcher, as we strongly believe that the notable boost in processor performance and efficiency along with its design simplicity makes Berti a serious candidate both for the emerging low-power edge market and for high-performance computers.

Host institution

UNIVERSIDAD DE MURCIA
Net EU contribution
€ 150 000,00
Address
AVENIDA TENIENTE FLOMESTA S/N - EDIFICIO CONVALECENCIA
30003 Murcia
Spain

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Region
Sur Región de Murcia Murcia
Activity type
Higher or Secondary Education Establishments
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Total cost
No data

Beneficiaries (1)