The first-ever mask-based technology for faster, precise, and sustainable printing of 3D interconnects for the display and semiconductor packaging industry.

Project Information

Impulse Printing

Grant agreement ID: 101189143

DOI

10.3030/101189143

EC signature date 8 December 2024

Start date 1 January 2025

End date 31 December 2026

Funded under

• The European Innovation Council (EIC)

Total cost

No data

EU contribution

€ 2 445 035,98

Coordinated by

FONONTECH HOLDING BV
Netherlands

Periodic Reporting for period 1 - Impulse Printing (The first-ever mask-based technology for faster, precise, and sustainable printing of 3D interconnects for the display and semiconductor packaging industry.)

Reporting period: 2025-01-01 to 2025-12-31

Summary of the context and overall objectives of the project

Advanced semiconductor packaging requires precise formation of conductive interconnects at scales ranging down to the micrometer size. Current manufacturing approaches rely predominantly on subtractive processes (lithography, etching) or additive nozzle-based dispensing. Subtractive methods generate significant material waste and require extensive chemical processing. Nozzle-based additive methods, while reducing waste, are limited to sequential deposition rates, creating production bottlenecks for high-volume manufacturing.
Impulse Printing addresses this throughput limitation through a mask-based parallel deposition technology. The technology enables simultaneous transfer of metallic materials from a printing plate to a substrate, achieving deposition rates of over100,000 interconnects per second. This represents a throughput increase of four orders of magnitude compared to sequential dispensing methods.
The project objectives are structured around two product categories: (1) Impulse Printing plates, which serve as the consumable transfer medium containing the deposition pattern, and (2) Impulse Printheads, which provide the controlled energy input for material transfer. The grant-funded activities target technology readiness level advancement from TRL 5 to TRL 7, focusing on scalable plate manufacturing processes, printhead productization, and industrial validation with semiconductor packaging customers.
The expected impact includes enabling European semiconductor manufacturers to adopt additive interconnect deposition without throughput penalties. Environmental benefits derive from reduced material consumption, elimination of chemical etching steps, and lower energy requirements per interconnect compared to conventional lithography-based processes.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

Work performed and main achievements
During the first reporting period (M1-M12), work concentrated on three parallel development tracks: baseline plate scalability, printhead productisation, and customer validation preparation.
Plate development (WP1, WP2): The baseline impulse plate manufacturing process was successfully scaled from laboratory-scale (50mm diameter) to production-relevant dimensions (200mm diameter). Process parameters for heater stack deposition, stencil patterning, and material loading were transferred to an external production facility. Initial production batches demonstrated print counts exceeding the minimum specification of 1,000 prints per plate. Work on high-resolution engraved plates (WP2) commenced with design iterations for feature sizes below 30 micrometres.
Printhead development (WP3, WP4): The baseline printhead underwent design modifications for improved serviceability and manufacturing repeatability. Thermal management subsystems were redesigned to support continuous operation cycles required for production environments. Documentation packages for printhead assembly and calibration were prepared to support future volume manufacturing.
Process validation (WP5): Collaboration with a European semiconductor manufacturer established baseline process parameters for a specific packaging application. Initial test prints demonstrated feature placement accuracy within specification. Preparation work for extended reliability testing was completed.
Infrastructure: Laboratory facilities were expanded to accommodate parallel testing of multiple printhead-plate combinations. Metrology capabilities were enhanced with automated print inspection equipment.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

The project has demonstrated two results that advance beyond current industrial capabilities for interconnect deposition:
High-power pulsed heating elements: The core technology relies on resistive heating elements that deliver energy in short pulses During the pulse, the heating elements achieve power densities surpass the power density at the surface of the sun. This extreme localised energy delivery enables rapid material transfer while limiting thermal exposure of the substrate. Due to the short pulse, the printhead uses less power than a lightbulb. Reliable operation at these power densities has been demonstrated across multiple plate production batches.
Massive parallel transfer capability: The printhead architecture was validated using an array of 256 independently addressable heating elements arranged in a 16×16 configuration, with each element measuring circa 8×8 mm. This parallel architecture enables simultaneous transfer across the full array in a single print cycle. When combined with substrate handling and stepping operations, the demonstrated configuration supports throughput rates in the range of millions of units per hour per machine. This throughput level exceeds sequential dispensing methods by approximately four orders of magnitude and approaches the production rates required for high-volume semiconductor packaging lines.
For continued technology uptake, establishment of volume plate manufacturing capacity is necessary to support multiple simultaneous customers in HVM manufacturing.