This report describes the progress at M12 of the 2D Pilot Line (2D-PL) project, which is the project’s first year. After the closure of the 2D Experimental Pilot Line (2D-EPL) we have progressed in our activities and worked towards meeting the overall project objectives. Building on the foundation established by the 2D-EPL, we continued to work on the project’s main objective: further maturing 2DM fabrication in an industrially relevant FAB environment to secure access to the 2D pilot line, with a focus on applications in photonics, electronics and sensors. To reach this goal, tool and material suppliers together with pilot line host partners have been working on testing, evaluating, optimising and designing novel materials, processes and hardware. Pilot line hosts have collaborated to optimise and compare best-known methods for making process modules, define and test measurement routines, and lay-out the foundation for collecting statistical relevant data sets in selected device and/or circuit architectures. Access to the pilot line is intended to allow external users to become acquainted with the novel technology under development, while simultaneously providing pilot line hosts insights from external validation of the offer. This includes both the set-up and sharing of the process design kits (PDKs) and the ability to participate in multi-project wafer runs (MPWs), enabling users to have their designs fabricated. To date, one hands-on training class has been hosted at imec (1-2 September 2025), offering three different PDK training sessions: graphene-based biosensors by GSEMI and AMO, photonic integrated circuits by IHP and Graphene on CMOS integration by VTT. Three MPW runs are open. Three MPW runs are open. Run 1, on “Biosensors & Liquid Biopsies” by GSEMI, focuses on graphene-based biosensors designed for liquid sample analysis, featuring passivated contacts to ensure stability in biological environments. Run 2 focuses on the development of “Graphene Photonic Integrated Circuits” (PIC) in a 200 mm pilot line, exploring various integration aspects for the realization of integrated devices, and is hosted by IHP. Run 3, hosted by VTT, is on “CMOS-Integrated Devices”, enabling the integration of graphene components with CMOS readout wafers to support scalable and low-power electronic applications.