Periodic Reporting for period 1 - DARE SGA 1 (Digital Autonomy for RISC-V in Europe (Specific Grant Agreement 1))
Período documentado: 2025-03-01 hasta 2025-08-31
Europe has fallen behind the US and Asia with respect to digital autonomy in High-Performance Computing (HPC), Artificial Intelligence (AI) and many other domains. Despite being a major consumer of silicon technology, Europe contributes less than 10% to the global value of silicon products. This market imbalance presents an opportunity for Europe to regain competitiveness by leveraging the emerging, open RISC-V Instruction Set Architecture (ISA), the advancements in chiplet technology, and the proliferation of open-source software. The main goal of the RISC-V ISA is to establish a standard, in contrast to the current situation where ISAs are owned by non-EU tech companies, locking end-users into their hardware and toolchains. Building on the RISC-V ISA offers Europe the potential to design and produce cutting-edge computational components while simultaneously advancing the RISC-V software ecosystem, contributing to the entire RISC-V community, and enabling the rapid migration of applications and system software to these new architectures.
The project, HPC Digital Autonomy with RISC-V in Europe or DARE, will take advantage of these technology trends, build on the current European RISC-V HPC research foundation (EPI, EUPILOT, eProcessor, and MEEP), as well as the results from previous Arm HPC initiatives originated from the Montblanc projects (EUPEX) and other related projects (e.g. DEEP-SEA), and add direct technology exploitation paths to create European HPC products for European supercomputers for research and industry. DARE proposes to build prototype HPC and AI systems based on EU designed and developed, industry-standard chiplets using the latest silicon technology nodes to meet the highest performance and energy efficiency requirements.
The project, HPC Digital Autonomy with RISC-V in Europe or DARE, will take advantage of these technology trends, build on the current European RISC-V HPC research foundation (EPI, EUPILOT, eProcessor, and MEEP), as well as the results from previous Arm HPC initiatives originated from the Montblanc projects (EUPEX) and other related projects (e.g. DEEP-SEA), and add direct technology exploitation paths to create European HPC products for European supercomputers for research and industry. DARE proposes to build prototype HPC and AI systems based on EU designed and developed, industry-standard chiplets using the latest silicon technology nodes to meet the highest performance and energy efficiency requirements.
In the first reporting period, most of the work was about preparing the grounds for the production, packaging, and integration of the three compute chiplets that are the main products that are going to be produced by the end of the DARE project. Towards that end, the technology node was selected to be at 4 nanometers, which is state of the art for high performance computing and AI accelerator designs. In a further step, the third party Intellectual Property (IP) acquisitions were negotiated. For the three chiplets, the architecture specifications were determined, and preparations for RTL coding of the compute blocks are initiated. A hardware/software co-design process helped to decide the architecture specifications, through a feedback loop process between the hardware and software teams. The architecture of the virtual prototype was worked on, and the first Software Development Vehicle (SDV) was made available for the application developers for functional testing of their code.
In the first reporting period, the project progress was mainly geared towards setting up the environment for chiplet production and integration, thus the achieved results are mainly towards the timely execution of the chjplet and prototype production which will be realized in the future reporting periods.
In this period, DARE defined the steps towards the prototype, delivered the system and chiplet architecture specifications comprising the prototype; described the scale-out approach, negotiated a bundle deal for indispensable third party glue-IP such as HBM, LPDDR and PCIe, selected the chiplet manufacturing technology node to be TSMC N4C, conducted a SW/HW co-design analysis which drove the architecture design choices, started the DARE Collaboration Council (DCC) and participated and contributed to RISC-V AI HW standardization efforts.
In this period, DARE defined the steps towards the prototype, delivered the system and chiplet architecture specifications comprising the prototype; described the scale-out approach, negotiated a bundle deal for indispensable third party glue-IP such as HBM, LPDDR and PCIe, selected the chiplet manufacturing technology node to be TSMC N4C, conducted a SW/HW co-design analysis which drove the architecture design choices, started the DARE Collaboration Council (DCC) and participated and contributed to RISC-V AI HW standardization efforts.