Europe has fallen behind the US and Asia with respect to digital autonomy in High-Performance Computing (HPC), Artificial Intelligence (AI) and many other domains. Despite being a major consumer of silicon technology, Europe contributes less than 10% to the global value of silicon products. This market imbalance presents an opportunity for Europe to regain competitiveness by leveraging the emerging, open RISC-V Instruction Set Architecture (ISA), the advancements in chiplet technology, and the proliferation of open-source software. The main goal of the RISC-V ISA is to establish a standard, in contrast to the current situation where ISAs are owned by non-EU tech companies, locking end-users into their hardware and toolchains. Building on the RISC-V ISA offers Europe the potential to design and produce cutting-edge computational components while simultaneously advancing the RISC-V software ecosystem, contributing to the entire RISC-V community, and enabling the rapid migration of applications and system software to these new architectures.
The project, HPC Digital Autonomy with RISC-V in Europe or DARE, will take advantage of these technology trends, build on the current European RISC-V HPC research foundation (EPI, EUPILOT, eProcessor, and MEEP), as well as the results from previous Arm HPC initiatives originated from the Montblanc projects (EUPEX) and other related projects (e.g. DEEP-SEA), and add direct technology exploitation paths to create European HPC products for European supercomputers for research and industry. DARE proposes to build prototype HPC and AI systems based on EU designed and developed, industry-standard chiplets using the latest silicon technology nodes to meet the highest performance and energy efficiency requirements.
