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MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems

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The influence of process variations is becoming extremely critical for nanoCMOS technology nodes, due to geometric tolerances and manufacturing non-idealities (such as edge or surface roughness, or the fluctuation of the number of doping atoms). As a result, production yields and figures of merit of a circuit such as performance, power, and reliability have become extremely sensitive to uncontrollable statistical process variations. Although some kind of variability has always existed and been taken into account for designing integrated circuits, the largest impact of variability and the greater influence of random or spatial aspects are setting up a completely new challenge. On top of those difficulties, the deficiency of design techniques and EDA methodologies for tackling PVs makes that challenge even more critical.
The objective of the MODERN project is to develop new paradigms in integrated circuit design which will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices.
Specifically, the main goals of the project are:
1. Advanced, yet accurate, models of process variations for nanometer devices, circuits and complex architectures.
2. Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performances.
- Reliability, noise, EMC/EMI.
- Timing, power and yield.
3. Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.
4. Validation of the modeling and design methods and tools on a variety of silicon demonstrators.
The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between industry and research institutes.

Wissenschaftliches Gebiet

Programm/Programme

Thema/Themen

Aufforderung zur Vorschlagseinreichung

JU-ENIAC-2008-1
Andere Projekte für diesen Aufruf anzeigen

Finanzierungsplan

JTI-CP-ENIAC - Joint Technology Initiatives - Collaborative Project (ENIAC)

Koordinator

STMICROELECTRONICS FRANCE
EU-Beitrag
€ 122 196,00
Adresse
134-136 AVENUE ARISTIDE BRIAND
92120 MONTROUGE
Frankreich

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Region
Ile-de-France Ile-de-France Hauts-de-Seine
Aktivitätstyp
Private for-profit entities (excluding Higher or Secondary Education Establishments)
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Letzte Aktualisierung: 27 Juni 2017

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Permalink: https://cordis.europa.eu/project/id/120003/de

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