Objetivo The objective of the HYETI project was to develop the design methodology, design tools and architecture necessary to achieve high yields on ULSI (Ultra Large Scale Integration) and WSI (Wafer Scale Integration) integrated circuits. The yield models, specialised architectures and focused CAD tools required for reconfiguration at the end of manufacture were to be studied in this project. Because defect densities in modern process technology are such that working wafer scale circuits can only be manufacturedby introducing redundancy into a chip, enabling the defects to be avoided by reconfiguration during production, this work was of high value. The need to produce a demonstrator to focus the many multi-discipline, interrelated facets of the WSI design problem was an important consideration from the start of the project. The objective of the project was to develop the design methodology, design tools and architecture necessary to achieve high yields on ultra large scale integration (ULSI) and wafer scale integration (WSI) integrated circuits. The yield models, specialised architectures and focused computer aided design (CAD) tools required for reconfiguration at the end of manufacture were to be studied in this project.As a conclusion to the work on yield analyses, the project found that the most satisfactory way to handle yield prediction for a specific topology is by graphic simulation. 2 architectures were selected for WSI implementation after a wide investigation: a 2-dimensional fast Fourier transform (FFT) processor and a processor array. After extensive investigation, the decision was taken during this preproject study to design and manufacture, in the follow up project, a 4 Mbit static random access memory (RAM), a systolic array and a reconfigurable 16-bit microprocessor.As a conclusion to the work on yield analyses, the project found that the most satisfactory way to handle yield prediction for a specific topology is by graphic simulation. Two architectures were selected for WSI implementation after a wide investigation: a 2-D Fast Fourier Transform (FFT) processor, and a processor array. After extensive investigation, the decision was taken during this pre-project study to design and manufacture, in the follow-up project, a 4 Mbit static RAM, a systolic array and a reconfigurable 16-bit microprocessor. As this was just a one-year pre-project to investigate the feasibility of WSI, only limited results were achieved. The work, with an adjusted workplan and modification in the partnership, has been continued under project 824. Ámbito científico engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringcomputer hardwarecomputer processorsnatural sciencesmathematicspure mathematicstopology Programa(s) FP1-ESPRIT 1 - European programme (EEC) for research and development in information technologies (ESPRIT), 1984-1988 Tema(s) Data not available Convocatoria de propuestas Data not available Régimen de financiación Data not available Coordinador SGS Thomson Microelectronics SA Aportación de la UE Sin datos Dirección 17 avenue des Martyrs 38340 Grenoble Francia Ver en el mapa Coste total Sin datos Participantes (8) Ordenar alfabéticamente Ordenar por aportación de la UE Ampliar todo Contraer todo BULL SA Francia Aportación de la UE Sin datos Dirección AVENUE DE MALAKOFF 75116 PARIS Ver en el mapa Coste total Sin datos British Telecom plc (BT) Reino Unido Aportación de la UE Sin datos Dirección British Telecom Laboratories Martlesham Heath IP5 7RE Ipswich Ver en el mapa Coste total Sin datos Brunel University Reino Unido Aportación de la UE Sin datos Dirección UB8 3PH Uxbridge Ver en el mapa Coste total Sin datos Cirrus Computer Ltd Reino Unido Aportación de la UE Sin datos Dirección 29-30 High Street PO16 7AD Fareham Ver en el mapa Coste total Sin datos Commissariat à l'Energie Atomique (CEA) Francia Aportación de la UE Sin datos Dirección Centre d'Études de Grenoble 17 avenue des Martyrs 38041 Grenoble Ver en el mapa Coste total Sin datos Institut National Polytechnique de Grenoble Francia Aportación de la UE Sin datos Dirección 38402 Saint-Martin-d'Hères Ver en el mapa Coste total Sin datos Institut National Polytechnique de Grenoble Francia Aportación de la UE Sin datos Dirección 46 avenue Félix Viallet 38031 Grenoble Ver en el mapa Coste total Sin datos Technische Hochschule Darmstadt Alemania Aportación de la UE Sin datos Dirección Schloßgartenstraße 64289 Darmstadt Ver en el mapa Coste total Sin datos