Skip to main content
Aller à la page d’accueil de la Commission européenne (s’ouvre dans une nouvelle fenêtre)
français fr
CORDIS - Résultats de la recherche de l’UE
CORDIS
Contenu archivé le 2024-04-15

High Yield and High Reliability ULSI System

Objectif

The objective of the HYETI project was to develop the design methodology, design tools and architecture necessary to achieve high yields on ULSI (Ultra Large Scale Integration) and WSI (Wafer Scale Integration) integrated circuits. The yield models, specialised architectures and focused CAD tools required for reconfiguration at the end of manufacture were to be studied in this project. Because defect densities in modern process technology are such that working wafer scale circuits can only be manufacturedby introducing redundancy into a chip, enabling the defects to be avoided by reconfiguration during production, this work was of high value.
The need to produce a demonstrator to focus the many multi-discipline, interrelated facets of the WSI design problem was an important consideration from the start of the project.
The objective of the project was to develop the design methodology, design tools and architecture necessary to achieve high yields on ultra large scale integration (ULSI) and wafer scale integration (WSI) integrated circuits. The yield models, specialised architectures and focused computer aided design (CAD) tools required for reconfiguration at the end of manufacture were to be studied in this project.

As a conclusion to the work on yield analyses, the project found that the most satisfactory way to handle yield prediction for a specific topology is by graphic simulation. 2 architectures were selected for WSI implementation after a wide investigation: a 2-dimensional fast Fourier transform (FFT) processor and a processor array. After extensive investigation, the decision was taken during this preproject study to design and manufacture, in the follow up project, a 4 Mbit static random access memory (RAM), a systolic array and a reconfigurable 16-bit microprocessor.
As a conclusion to the work on yield analyses, the project found that the most satisfactory way to handle yield prediction for a specific topology is by graphic simulation.
Two architectures were selected for WSI implementation after a wide investigation: a 2-D Fast Fourier Transform (FFT) processor, and a processor array. After extensive investigation, the decision was taken during this pre-project study to design and manufacture, in the follow-up project, a 4 Mbit static RAM, a systolic array and a reconfigurable 16-bit microprocessor.
As this was just a one-year pre-project to investigate the feasibility of WSI, only limited results were achieved. The work, with an adjusted workplan and modification in the partnership, has been continued under project 824.

Champ scientifique (EuroSciVoc)

CORDIS classe les projets avec EuroSciVoc, une taxonomie multilingue des domaines scientifiques, grâce à un processus semi-automatique basé sur des techniques TLN. Voir: Le vocabulaire scientifique européen.

Vous devez vous identifier ou vous inscrire pour utiliser cette fonction

Programme(s)

Programmes de financement pluriannuels qui définissent les priorités de l’UE en matière de recherche et d’innovation.

Thème(s)

Les appels à propositions sont divisés en thèmes. Un thème définit un sujet ou un domaine spécifique dans le cadre duquel les candidats peuvent soumettre des propositions. La description d’un thème comprend sa portée spécifique et l’impact attendu du projet financé.

Données non disponibles

Appel à propositions

Procédure par laquelle les candidats sont invités à soumettre des propositions de projet en vue de bénéficier d’un financement de l’UE.

Données non disponibles

Régime de financement

Régime de financement (ou «type d’action») à l’intérieur d’un programme présentant des caractéristiques communes. Le régime de financement précise le champ d’application de ce qui est financé, le taux de remboursement, les critères d’évaluation spécifiques pour bénéficier du financement et les formes simplifiées de couverture des coûts, telles que les montants forfaitaires.

Données non disponibles

Coordinateur

SGS Thomson Microelectronics SA
Contribution de l’UE
Aucune donnée
Adresse
17 avenue des Martyrs
38340 Grenoble
France

Voir sur la carte

Coût total

Les coûts totaux encourus par l’organisation concernée pour participer au projet, y compris les coûts directs et indirects. Ce montant est un sous-ensemble du budget global du projet.

Aucune donnée

Participants (8)

Mon livret 0 0