Obiettivo
- A market survey will be performed to determine which FPGA product family will best suit the model application.
- A market survey will be performed to determine which design tools will allow a maximum of flexibility and independence of a specific manufacturer and/or ASIC/FPGA product family.
- Using one sample design, experience shall be gained how to transfer from a gate level description to a VHDL description for the purpose of portability.
- Evaluating two sets of design tools and two different FPGA product families experience shall be gained on design productivity and efficiency ( design cost, product cost ).
- Design methods and rules will be determined to ease future retargetting activities.
- The retargetted design will be simulated to a confidence level allowing a follow-on activity for production implementation.
With ASIC technology being improved every year, 'old' manufacturing processes are phased out and chip designs have to be retargetted to new processes. For applications with a low series production volume, the non-recurring costs of gate array redesign add a significant contribution to the product price.
As today cheap FPGAs are available in complexities that were reserved for gate array design some years ago, devices, tools, and methods will be evaluated to transfer from gate array technology to FPGAs for such applications. The tools and methods will further allow a high flexibility in future selection of device types, manufacturers, and technology.
Campo scientifico
Invito a presentare proposte
Data not availableMeccanismo di finanziamento
ACM - Preparatory, accompanying and support measuresCoordinatore
60388 Frankfurt
Germania