Final Activity Report Summary - CANADEVICE (Development of IC devices based on carbon nanotubes and nanowires)
At the onset of the project, the major focus of the international research on carbon nanotubes (CNTs) and nanowires was on improving the characteristics of CNTs and nanowires themselves. The researcher took the next step by proposing a viable nano-electronics product for both nanostructures, respectively CNT-based interconnects and nanowire-based heterostructure tunnel field-effect transistors (FETs). A prototype of both devices was realised on wafer-scale. Many possible CNTs applications were proposed, from fire-proof blankets, reinforced tennis rackets and electrically conductive plastics to field emitters for flat-panel displays, sensors, FETs and interconnects.
The researcher investigated in full detail the potential of those applications that were closest to the expertise of the host institution 'Interuniversitair Micro-electronica Centrum VZW' (IMEC), namely FETs and interconnects. She concluded that a CNT-based FET could not currently be mass-fabricated, since there was no control over the CNT type (there existed hundreds of different CNTs) which was produced at any particular location. On the other hand, she showed that CNT-based interconnects were feasible and had the potential to beat the existing copper-based interconnects, provided that high-quality CNTs could be grown at extremely high densities. Supporting her analysis with simulations, she showed that both the interconnect delay and dynamic power, the most important figures of merit of respectively global and local interconnects, could be decreased significantly upon using CNTs. At the same time, CNT-based via allowed for drastic reductions in the chip temperature, because of the CNTs high thermal conductivity.
With these predicted benefits, the team of CNT-growth experts started working towards the challenging geometrical specifications of extremely high density CNTs on wafer-scale in via holes. A prototype of such a CNT-based interconnect was realised and characterised. As part of the characterisation effort, an optimised initialisation procedure, which improved the electrical contact between metal and CNT, was developed.
The proposed applications of semiconducting nanowires ranged from nano-photonics devices to nanowire-based sensors and from conventional metal-oxide-semiconductor FETs (MOSFETs) to more quantum-effect-based FET concepts. The researcher investigated in full detail the potential of those applications that were closest to the expertise of the host institution IMEC, namely FETs. She concluded that, even though there was an improvement in the MOSFET characteristics because of the better gate control in a nanowire-based MOSFET configuration, the improvement was too incremental to induce a full technology change from a planar to a vertical nanowire-based technology. On the other hand, a novel FET-concept, namely the tunnel-FET (TFET), had the potential to introduce a disruptive technology when based on heterostructure nanowires. The major advantage of the TFET was its unlimited sub-threshold swing, which allowed for significantly reduced power consumption.
The researcher deepened the existing insight in the TFETs characteristics by her investigation of both gate modifications and source-material modifications on the TFET performance. She demonstrated, through device simulations, that source-material modifications resulting in a heterostructure TFET could boost the on-current of the otherwise silicon TFET to the same level as the MOSFET, while maintaining the other TFET advantages. This result removed the major drawback of the silicon-based TFET, namely its low on-current, and allowed the TFET to fully compete with the MOSFET. In a subsequent study, the researcher successfully addressed the next major issue of TFETs, namely the lack of a heterostructure p-TFET. A set of complementary FETs was a key requirement in order to perform logic with manageable static power consumption.
Motivated by the anticipated potential of the TFET, a team of growth experts started working towards the wafer-scale implementation of nanowire-based TFETs. A prototype of such a device was very recently constructed and characterised. As part of her analysis effort, the researcher developed a semi-analytical model for the TFET performance.
The researcher investigated in full detail the potential of those applications that were closest to the expertise of the host institution 'Interuniversitair Micro-electronica Centrum VZW' (IMEC), namely FETs and interconnects. She concluded that a CNT-based FET could not currently be mass-fabricated, since there was no control over the CNT type (there existed hundreds of different CNTs) which was produced at any particular location. On the other hand, she showed that CNT-based interconnects were feasible and had the potential to beat the existing copper-based interconnects, provided that high-quality CNTs could be grown at extremely high densities. Supporting her analysis with simulations, she showed that both the interconnect delay and dynamic power, the most important figures of merit of respectively global and local interconnects, could be decreased significantly upon using CNTs. At the same time, CNT-based via allowed for drastic reductions in the chip temperature, because of the CNTs high thermal conductivity.
With these predicted benefits, the team of CNT-growth experts started working towards the challenging geometrical specifications of extremely high density CNTs on wafer-scale in via holes. A prototype of such a CNT-based interconnect was realised and characterised. As part of the characterisation effort, an optimised initialisation procedure, which improved the electrical contact between metal and CNT, was developed.
The proposed applications of semiconducting nanowires ranged from nano-photonics devices to nanowire-based sensors and from conventional metal-oxide-semiconductor FETs (MOSFETs) to more quantum-effect-based FET concepts. The researcher investigated in full detail the potential of those applications that were closest to the expertise of the host institution IMEC, namely FETs. She concluded that, even though there was an improvement in the MOSFET characteristics because of the better gate control in a nanowire-based MOSFET configuration, the improvement was too incremental to induce a full technology change from a planar to a vertical nanowire-based technology. On the other hand, a novel FET-concept, namely the tunnel-FET (TFET), had the potential to introduce a disruptive technology when based on heterostructure nanowires. The major advantage of the TFET was its unlimited sub-threshold swing, which allowed for significantly reduced power consumption.
The researcher deepened the existing insight in the TFETs characteristics by her investigation of both gate modifications and source-material modifications on the TFET performance. She demonstrated, through device simulations, that source-material modifications resulting in a heterostructure TFET could boost the on-current of the otherwise silicon TFET to the same level as the MOSFET, while maintaining the other TFET advantages. This result removed the major drawback of the silicon-based TFET, namely its low on-current, and allowed the TFET to fully compete with the MOSFET. In a subsequent study, the researcher successfully addressed the next major issue of TFETs, namely the lack of a heterostructure p-TFET. A set of complementary FETs was a key requirement in order to perform logic with manageable static power consumption.
Motivated by the anticipated potential of the TFET, a team of growth experts started working towards the wafer-scale implementation of nanowire-based TFETs. A prototype of such a device was very recently constructed and characterised. As part of her analysis effort, the researcher developed a semi-analytical model for the TFET performance.