Final Report Summary - EUROPIC (European Manufacturing Platform For Photonic Integrated Circuits)
Executive summary:
The EUROPIC project was set up to facilitate access by small companies to cost-effective indium phosphide based photonic integrated circuit (PIC) manufacture in Europe. Its objective was no less than to effect a fundamental change in the way applications based on PICs are designed and manufactured in Europe. This was to be achieved by developing a generic technology that is capable of realizing complex PICs from a small set of basic building blocks; a production model well known in micro-electronics where complex electronic circuits are built from standardized transistors and a small number of other elements.
The programme adopted a holistic approach, addressing the whole production chain from idea, via proof of concept, design and prototype to product and application. Research has been carried out into manufacturing methods and high-throughput processes, which will lead to an open-access industrial generic foundry production capability for Europe. The EUROPIC generic platform for manufacturing of PICs is based on InGaAsP materials technology (generally referred to as InP technology) which gives access to operating wavelengths typically used in telecommunications approximately 1.3 μm - 1.55 μm. EUROPIC has both set up the first generic foundry for InP-based PIC production in an industrial environment; and demonstrated its viability for small and medium-sized enterprises (SMEs). It has demonstrated the potential of the generic approach by fabricating a number of application specific PICs (ASPICs) concurrently on the same wafer- with high levels of complexity and performance, for a wide range of applications in telecommunications, sensors, data communications, medical systems, metrology and consumer photonics.
The completion of the EUROPIC programme heralds the start of a new chapter in the production of photonic integrated circuits. EUROPIC has not only successfully undertaken the first generic foundry run based on industrial (commercial) fabrication facilities at Oclaro (in the United Kingdom (UK)) and at FhG-HHI (in Germany), but also put in place most of the other elements of the production chain required to deliver it, and this for the first time.
Further, EUROPIC has built a strong user group, many of them SMEs, with committed users from different application fields, who will be actively involved in introducing cost-effective ASPICs in a variety of novel applications in the future, providing Europe with a competitive advantage over the United States (US) and the Far East.
Today, Europe's lead in this branch of photonics is clear, and InP-based PIC technology stands ready for full commercialisation.
Project context and objectives:
A summary description of project context and objectives.
Context
The EUROPIC project aimed to facilitate access by small companies to cost-effective InP-based PIC manufacture in Europe by setting up a generic fabrication platform based on industrial fabs.
At the beginnings of EUROPIC, it could be observed that despite large investments through national and international projects in Europe, America and the Far East, integrated photonics had far from fully redeemed its promises. The problem which EUROPIC set out to address was that the dominant working method in photonics was to develop optimised fabrication processes for each and every application, starting from the specifications of the product. As a result of this approach, there exist now almost as many fabrication technologies as applications. Due to this huge fragmentation in fabrication processes in relation to the associated market sizes, the cost price per product is far too high for a successful and sustainable introduction of products based on or including photonics components. In particular, the cost of entry is too high for most businesses. In order to create the breakthrough of photonics in a wide variety of application fields both the development cost and the unit cost need to be brought down by at least an order of magnitude.
The EUROPIC response was to create generic integrated technology for the research, development and manufacturing of ASPICs. Instead of optimising the fabrication technology for every specific application, the product design would be adapted to the capabilities of available, mature, high performance fabrication processes. This solution seems obvious in retrospect; we should introduce the same methodology to photonics that allowed micro-electronics to change the world since the eighties with CMOS technology.
CMOS, where a huge number of functions is reduced to a few elementary functions, which are performed by elementary building blocks like transistors, diodes, resistors and capacitors fabricated in a generic process, supports integration of these elementary building blocks in large numbers and in different circuit topologies. Therefore CMOS is capable of realising a wide variety of functions (chips) for a very broad range of applications. The fabrication processes can be made available via foundries to a large number of designers who use powerful design kits that allow fast and accurate design of the chips. In this way the large investments in development of the high-performance foundry processes can be shared by a large number of applications, resulting in a low cost price per product, thus enabling the current ubiquity of electronic integrated circuits.
Competing technologies for photonic integration have also advanced over the four years since the EUROPIC objectives were written; notably Si-photonics and the passive dielectric platform TriPleX. Silicon based photonics for example has demonstrated several key building block developments in the last few years using various technologies, but integration of these into the same CMOS compatible platform remains a significant challenge as does the provision of an on-chip optical source with reasonably high output power. The InP platform remains in a strong competitive position, and has high complementarity with the capabilities of Triplex.
Generic process
EUROPIC has addressed core aspects of this process chain, ranging from PIC design to consideration of approaches to generic packaging.
The methodology the consortium has applied to reach its project goals is:
- to decompose the functionality of complex photonic micro-systems into a small set of basic functions;
- to develop a building block for each of the basic functions and to develop production processes that are capable of integrating the basic building blocks in any arbitrary combination and number;
- to develop a dedicated design kit that contains an accurate model of the performance of the basic building blocks and that can simulate the response and the performance of complex circuits built from these building blocks as well as generate the mask layout;
- to develop dedicated measurement tools and vehicles for testing the quality and performance of the basic building blocks, in such a way that testing the performance of complex circuits is reduced to proper testing of the basic building blocks;
- to test the foundry concept with examples of high complexity ASPICs;
- to develop a small set of generic packages that can be used for a broad class of PICs, by introducing standardisation in the positions of optical and electrical connections, in chip dimensions and positioning of heat generating elements, which allows designers to work with them to work seamlessly in the design environment.
This methodology has been applied to two platforms, based on PIC fabrication, at the Fraunhofer HHI, Berlin and at Oclaro, UK respectively. It has delivered a generic integration technology at both.
Objectives
The project has achieved, or made significant progress, in all aspects of its initial objectives. In summary the project aimed to:
- to bring the application of photonic integrated micro-systems with a high added value in advanced products within reach for a broad class of SMEs by reducing the entrance costs dramatically by more than one order of magnitude;
- to enable the emergence of a new field of research in circuit-based photonic devices with ever increasing complexity and performance.
To demonstrate this, a number of target application PICs were produced, some constituting hero experiments in the technology, with a record combination of complexity and performance realised in a vastly reduced development time:
- to investigate novel technologies for extending the functionality supported by a basic manufacturing process;
- to shorten the R&D cycle time significantly by developing a software design kit with accurate models of the basic building blocks and their performance;
- to develop a generic test methodology that allows for a significant reduction of the effort required for testing and qualification, by testing the basic building blocks rather than specific PICs;
- to develop a generic packaging approach that allows for packaging a variety of different PICs with a small set of standardised packages;
- to develop a business model for a rapid but evolutionary introduction of the generic foundry approach in a number of application fields, mainly by and for SMEs.
Status
EUROPIC has not only successfully undertaken the first generic foundry run based on industrial (commercial) fabrication facilities at Oclaro (in the UK) and at FhG-HHI (in Germany), but also put in place many of the other elements of the production chain required to deliver this capability, and this for the first time. It has investigated new process methodologies and technologies capable of platform introduction in the future and new routes to generic packaging, going on to fabricate ASPICs of significant complexity and performance.
The ASPICs which result can take many forms, from a few basic building blocks such as waveguides, detectors, amplifiers and phase modulators to complex photonic chips with hundreds of building blocks can be designed and fabricated.
Project results:
Technical achievements
State of the art (start of project) EUROPIC target - Progress
- Developing specific manufacturing technology for each new PIC application
- Demonstration of the feasibility of a generic integration technology that allows for R&D&M of ten integrated micro-systems with a high added value for application in advanced photonic products.
- Chip development costs in multi-M- range even for relatively simple devices - Generic integration methodology to allow chip development cost reduction by at least one order of magnitude.
- Chip development timescales of several years - Put in place design tools and methodology to allow chip development times less than one year.
- PIC applications mainly in telecoms - Broaden applications to sensors, health, datacom, instrumentation, signal processing, and more.
- Few SMEs involved in new photonic device development - 100 SMEs involved in design and development of products containing novel photonic devices- 100 - strong user group. (Not all SMEs)
- Technology development slow despite large investment scceleration of technology development speed because of focused investment on a small set of broadly applicable technologies.
Objectives
EUROPIC has been successful or made significant progress against all of its objectives. The project has:
- successfully established the software-design-foundry work flow chain;
- software design kit built to support generic platform operation. The design kit features physical layer models and mask layout software. Integrated BB descriptions;
- platform supported by design manual for InP photonic circuits;
- circuit models ported through an API between different elements of the design toolkit;
- carried through the first generic platform run for InP PICs in Industry a key enabling step to achieve the programme objectives discussed above;
- approximately 20 different ASPIC designs realised on the platform with state-of the art complexity, plus 5 external user designs. Application level exploitation and demonstration of technology access for SMEs;
- demonstrated full BB transfer cycle onto the platform for AWG technology (both at FhG-HHI and Oclaro).
Another key objective for the project opening the path for future platform transfers. The project has also advanced several other technologies towards platform status; a theme which is expanded upon below.
- Worldwide awareness of photonic foundry operation raised significantly. But further technical work remains to be done to bring the platform to commercial realisation.
- Wafer validation (establishing the compliance of the finished wafer with accepted platform performance standards) - methodology not yet fully established.
- BB design data is still sketchy in places - more detailed and comprehensive building block characterisation is required.
- Generic test. Approaches to bar level test developed at Oclaro Technology have not yet worked through to full measurement data sets.
- Generic packaging chip daughterboard approach demonstrated. Generic design rules established. Performance (alignment accuracy) not yet established. Daughterboard motherboard integration (should be the simpler step) not yet demonstrated.
- Procedural / organisational aspects of the generic fab.
Generic fab concept
EUROPIC has created for the first time a foundry process for InP based photonic integrated circuits using industrial InP fab processes. A crucial aspect for photonic circuit designers has been to put in place a design environment to support easy access to the platform technology. In this technical report, we outline the technology which makes the InP based generic fab a reality.
Multi-project wafer runs
The methodology the consortium has applied is:
- to decompose the functionality of complex photonic micro-systems into a small set of basic functions;
- to develop a building block for each of the basic functions and to develop production processes that are capable of integrating the basic building blocks in any arbitrary combination and number;
- to develop a dedicated design kit that contains an accurate model of the performance of the basic building blocks and that can simulate the response and the performance of complex circuits built from these building blocks, as well as supporting mask layout;
- to develop dedicated measurement tools and vehicles for testing the quality and performance of the basic building blocks, in such a way that testing the performance of complex circuits is reduced to proper testing of the basic building blocks;
- to test the foundry concept with examples of high complexity ASPICs.
This methodology, which has been applied to two platforms, based on PIC fabrication at the Fraunhofer HHI, Berlin and at Oclaro, UK, has delivered a generic integration technology at both. At the conclusion of EUROPIC the HHI supported process is a receive side platform with passive components and a 40 GHz detector capability. The Oclaro platform meanwhile has a full transmit / receive capability but at 10 GHz.
Decomposition of the foundry process into elementary building blocks, and some more complex composite blocks, enables different ASPIC designs to be easily designed on the same platform and compiled into a single run a multi-project wafer run. The developed design environment, including all the software developments and definition of building blocks based on generic photonic integration technologies, has been extensively used and tested in such multi-project wafer runs (MPW run) and more than twenty different designs have been successfully created, originating from a wide variety of users, ranging from SMEs, research institutes, universities and large companies, and fabricated in separate runs by Oclaro and HHI.
EUROPIC design environment
Central to the operation of the design environment is the photonic design automation flow API - application programmers interface (PDAFlow API). The API created by EUROPIC contains the interface elements which enable physical layer design tools, such as Aspic from Filarete and PICWave from photon design, to work together with PhoeniX design tools and mask layout tools as if they were all part of an integrated package. The PDAFlow library also contains the calibrated building block descriptions for each platform.
The design environment
The design environment comprises the software environment, the design manual and the technology specific design kits. In the EUROPIC project, multi project wafer (MPW) runs for PICs fabricated in indium phosphide have been successfully implemented with the support of a design environment as created by partners Photon Design (UK), Filarete (Italy) and PhoeniX (the Netherlands). The software partners have developed a common platform to define photonic libraries and adopted their software solutions like PicWave, Aspic and MaskEngineer to be able to use these libraries or design kits for above named manufacturing sites. This has been done in close collaboration with the InP foundries at Oclaro and HHI.
The design kits contain all relevant information for designers to create a photonic integrated device or circuit within the capabilities of the fabrication processes. Users benefit from this by having immediate access to mature and proven building blocks, ensuring functional devices.
PDA flow API
One of the key aspects of this development has been to achieve interoperability of the software elements within the design environment. In the EUROPIC design kit, rather than having one very large and inflexible single piece of software, the unique properties and advantages of the different software packages are maintained. This allows for easier extension towards new software partners and also provides for a robust future proof approach. The required new approach is therefore that of being able to have the software elements 'talk together'; in software terminology an application programmers interface (API) for short.
Although the concept of an API is well established, both in general software engineering and applied in micro-electronics software tooling, this was not yet the case in micro-photonics. The EUROPIC project partners have developed a photonics domain specific API, called the PDAFlow-API. After the EUROPIC project end, this API has been be transferred to the ICT project PARADIGM (Seventh Framework Programme (FP7) ICT project No. 257210) for further development and in the near future it will be made available as a de-facto standard to interested parties through an independent foundation.
Design kits
Building blocks containing the geometrical information such as parameters, boundaries, design rules, intellectual property rights, simulation settings, mask information, and release version, have been created within the project. These building blocks give a designer the capability to design at a high abstraction level by using these 'standard' elements, provided by the manufacturing parties. In addition one can add additional constraints to this design, for instance by adding the boundary conditions imposed by the allowed chip sizes, package templates or packaging method. These building blocks are provided to the designers within the design environment, consisting of the software environment, the design manual and the technology specific design kit.
Design manual
An essential ingredient in the process flow is the design manual which enables the designer to access quickly the building blocks available in the platform. Design rules and standardised templates for packaging layouts are all supplied in the design manual and configured in the design tools for ease of use.
The design manual is one of the most critical achievements of the project. It encapsulates the foundry processes in a way which makes the technology immediately accessible to PIC designer; it has already been instrumental in enabling groups independent of EUROPIC to design onto the platforms.
API legal
During the EUROPIC project, a clear interest from groups outside the consortium was already visible and the results obtained within the project indicate the usefulness of the developed API for the future.
To optimally exploit the developed capability, use of the API will be extended as widely as possible within the photonics community, and since multiple definitions and/or multiple competing APIs would, if such existed, hinder the development of a successful photonics eco-system, the three key software parties in the consortium, Filarete, Photon Design and PhoeniX software have fixed upon the creation of a single legal entity to control the development and licensing of the PDAFlow API. A not for profit organisation will be created, structured as a legal entity in the Netherlands, a so called 'Stichting'. It is expected that the finalisation of the set-up of this 'Stichting' will take about four months from the end of the EUROPIC project. Contacts have already been established with potential partners both inside and outside the photonics field, which will allow a quick uptake into the academic community as well as with commercial software groups worldwide. At the time the legal entity is finalised, announcements will be made to the photonics community and one-on-one communication with relevant parties continued and new discussions initiated.
InP platform technology
EUROPIC has two InP fab partners, Oclaro and FhG-HHI, prepared to take up the challenging task of platform development. FhG-HHI can rely on a long-standing broad expertise in InP photonics technology. In particular, it reported the world's first fully integrated heterodyne receiver PIC as early as in 1994: at that time it was the most complex PIC ever made. FhG-HHI is now a world leader in high-speed receivers, amongst others. Oclaro has also long been a leader in this field, having published many innovative PIC designs and research results going back to the early 1990s, and many of Oclaro's advanced telecommunications products presently incorporate InP PIC technology.
Process research and exploitation in InP-based photonics requires access to world class fabrication facilities and these partners have opened up access to their production lines for this project.
Oclaro's clean rooms support a full-scale manufacturing facility at Caswell, UK, offering 57 000 ft2 (19 000 ft2 at class 10/100) of process space dedicated to a 3 InP process capability with a capacity exceeding 6000 wafers/year. The Caswell fab is one of the largest and best-equipped facilities worldwide dedicated to optoelectronic devices and circuits. Amongst the various process tools we may note six multi-wafer MOVPE reactors, e-beam lithography, plasma etch and deposition tools and extensive on-line control and diagnostic facilities.
FhG-HHI has successfully developed a wide range of different photonic devices (amongst them various types of laser diodes, ultra-fast photo-detectors, high-bit rate modulators, components for all-optical signal processing), in many cases in close cooperation with domestic and foreign SMEs. In offering PIC foundry developments and trial services FhG-HHI, through its photonic components department, brings into the project its entire R&D InP processing line comprising amongst many others such expensive equipment as a newly installed multi-wafer MOVPE reactor (8 x 2- 4), and a high resolution electron beam lithography apparatus.
In addition other composite elements are available such as AWGs. In this project there has been a strong focus on compatibility between building blocks in order to build optical circuits.
While both of the two platforms of Oclaro and FhG-HHI use 3 InP wafer technology, there are to-date still distinct technological differences; whereas Oclaro's platform builds on electrically conductive n+-substrate starting from their established and world-leading tunable laser and electro-optic modulator technology, FhG-HHI is using semi-insulating substrates (InP:Fe) starting from their proven high-speed waveguide-integrated photodetector technology. Accordingly the former platform mainly supports transmit and lower-frequency receive functions (10 GHz), whereas HHI's platform is focused on receiver-type PICs capable of 40 GHz bandwidth.
Application specific photonic integrated circuits realised
It was the aim of the project to validate the generic foundry approach by testing the whole production chain; the functionality and performance of the building blocks, the software design tools, the generic packaging and the viability of a set of challenging applications. With that aim two so-called multi-project wafer (MPW) runs have been scheduled in the project, one halfway and one at the end of the project. They have been carried out in the generic integration processes developed by EUROPIC partners Oclaro and Fraunhofer-HHI. MPWs are wafers on which a large number of ASPICs are combined in a single mask set and processed in a single wafer run. This concept, which is well known in micro-electronics, leads to a large reduction in R&D and product entry costs.
ASPICs from the first MPW-run became available in 2011. First results were very encouraging and have been published at a number of conferences (OFC 2012, ECIO 2012, CLEO 2012). A second MPW run, which contained both new ASPICs and improved redesigns of a number of the original ASPICs, has just completed fab at the end of the project. With these MPW-runs, which are the world's first InP-based generic foundry runs, EUROPIC has demonstrated the potential of the generic foundry model to bring photonic ICs within reach for many SMEs and large companies, by a dramatic reduction of the entry costs for developing complex photonic ICs.
Generic packaging of ASPICs in EUROPIC
Generic technology at the chip level requires a generic packaging approach which can accommodate most of the requirements set by chip designers for dc electrical, RF and optical I/O. In EUROPIC our approach has been based on the use of CIP's HyboardTM approach. Hyboard uses a patterned daughterboard made of silicon to carry the InP chip which is then positioned on a motherboard containing silica waveguides. The parts are then aligned passively. The fabrication of motherboards and daughterboards uses CIP's standard etching techniques for the daughterboards and flame hydrolysis deposition of silica on silicon for the motherboards. The designs have been developed in close collaboration with the InP PIC designers. They are used to package InP chips in the following way: the InP chip is flip chip bonded to the daughterboard, and this is then flipped again on to the motherboard. All the electrical connections are handled by the daughterboard, while all the optical interfaces are handled by the motherboard. The motherboard and daughterboards have been designed to be generic for all InP chip designs, provided a set of design constraints is followed. The exception to this is that the daughterboard metallisation is specific to a chip design, and is therefore laid out by the InP chip designer using a set of design rules to make it compatible with the daughterboard.
New semiconductor technology development
The generic platform technology must not be frozen in time, but should develop alongside the requirements of the users. EUROPIC has identified several technologies valuable in platform enhancement. The project has investigated the transfer of technology (building blocks) from an R&D base onto the platforms both at HHI and Oclaro in a number of specific cases. One can identify six maturity levels in new technology introduction onto the platform.
1. No established technology position in consortium
2. Demonstration at a technology house in the consortium
3. Technology assessed as ready to transfer as a building block
4. Demonstration of the building block in the platform process
5. Use in an ASPIC design by a circuit designer
6. ASPICs fabricated and tested using new BB
Building block- EUROPIC start- EUROPIC end
AWG technology BB - Level 2 - Level 6
Selective area growth (SAG) - Level 1 for Al(Q) - Level 3 continuation of technology platform introduction within PARADIGM project
Use of Al(Q) material - Level 2 - Level 4 - Use of Al(Q) for improved temperature performance will become standard in future platform releases.
Low PDL SOA based on Al(Q) - Level 1 - Level 3 - Source material demonstrated which can be fed into the platform at process start.
Polarisation rotators - Level 2 - Level 2/3 continuation of technology development within the PARADIGM project
Lasers on SI substrates (at HHI) - Level 1 - Level 4 (full platform introduction of the laser building block is an important part of the PARADIGM programme at HHI
Development of the platform at circuit level
Platform technology is multi-layered. New building blocks can be transferred into the platforms by the fab specialists whilst designers, independent of the underlying fab technology, can develop their own IP on the platform through the development of not just ASPIC designs, but also new building blocks, composites and photonic circuit libraries within the design environment. A good example of such a development within EUROPIC concerns the arrayed waveguide grating based devices.
Arrayed waveguide filters and multiplexers
A very important component in integrated optics is the arrayed waveguide grating (AWG). This component, effectively a prism, spatially (de)multiplexes light of different wavelengths in a photonic integrated circuit. The large number of constituent parts in AWGs and the required uniformity makes them very complex (circuit level) components.
The TU Eindhoven group has a long history with AWGs, dating back to their invention, and a lot of experience in the design and manufacture of this component. Within the EUROPIC project, a transfer of those capabilities to the Oclaro platform was achieved. In addition, the now commercially available BrightAWG module was successfully ported and tested in EUROPIC on the Oclaro and HHI platforms (it is also compatible with silicon on insulator (SoI) technology), and the resulting composite building block implemented in the design manual to allow easy access for designers. The result was excellent components that have already found their way into over 20 ASPIC designs within the EUROPIC project.
New business model
The separation of function with the generic fab leads to a new business model with the added advantage of clarification of legal responsibilities and IP ownership. Chip technology remains clearly owned by the fab and embedded calibration data can be hidden from the user in the software tools if necessary. Equally the fab can be application blind and as long as a circuit is platform compliant it can be fabricated without the fab having specific knowledge of its function. For immediate use, EUROPIC has developed an NDA; a one-to-many agreement, for use between the consortium and interested platform users.
New technology
Platform technology cannot stand still; it should evolve alongside the requirements of the user community. Major revisions and releases of new fab technology can occur on an occasional basis according to the platform roadmap (this point is covered in the subsection below). However, EUROPIC has also explored how new composite building blocks can be developed from existing ones (such as AWGs from passive waveguide building blocks) and how new technology building blocks can be introduced into the platform on a more evolutionary basis. Starting from a different technology provider partner there is a link formed with a fab partner to establish if a new BB can be platform compatible, and to fully characterize it. In addition, those responsible for the software design kits need to integrate the new capability into the design environment to make it available to the designers. A good example of such a development is the work on selective area growth which can extend the platforms to cover new wavelengths or extended wavelength ranges on a wafer.
Roadmaps
Working through JePPIX a roadmap for the generic fab development has been published for 2012.
The roadmap foresees first exploitation of the generic fab commercially through 2014 - 2015; however, the JePPIX platform and the fabs are already in close discussion about quasi-commercial activity to further trial the EUROPIC platform in 2013.
Summary
The EUROPIC consortium has taken an important first step in setting up a generic technology platform for ASPICs in InP using all industrial / commercial elements. Many successful designs have already been realised by project partners and a few by external groups trialing the platform. We stand at the threshold of commercialisation for this important technology.
The platform organisation JePPIX (the JePPIX coordinator is Luc Augustin, coordinator@jeppix.eu via e-mail) continues to promote the platform activities in Europe, whilst the ICT PARADIGM project seeks to extend the capability of the platforms through new technology introduction such as extensions to a full transmit and receive, and to a 40 G capability, also embracing a wider range of wavelength of operation.
Potential impact:
Potential impact of the EUROPIC project
We are confident that EUROPIC has already made a significant impact in many different spheres:
- academia through publications and invited talks;
- SMEs, large companies and academia through the user group and newsletters;
- web presence (websites of EUROPIC and JePPIX);
- social networking presence (LinkedIn);
- business potential through JePPIX and GPICsLab;
- personal contacts.
This view of a rapidly increasing level of interest in the generic fab is supported both by developments in the PARADIGM project where a very recent call for new users has attracted in excess of forty design proposals, and in the number of invited presentations at international conferences.
Introduction
PICs have shown an impressive increase in performance and complexity over the last two decades. But of the many components that have been investigated and reported by academic and industrial research labs very few have reached the commercial stage, so far. The main reason is that development of PICs is very expensive and large markets (typically well beyond 100 000 pieces) are required to pay back for the required investment. Such large markets can only be served by big companies, and even for them the commercial risks are high.
EUROPIC has aimed at investigation and experimental demonstration of a novel production paradigm that leads to a dramatic reduction of PIC research, development and manufacturing (R&D&M) costs by more than an order of magnitude. The expected cost reduction is such that it will bring the application of PICs in a variety of advanced products within reach for many SMEs. By doing this it lays the foundation for a dramatic expansion of the application spectrum and the market volume of PICs and novel or improved products that are enabled by or gain a competitive advantage by applying PICs for low-cost integration of complex functionality.
The EUROPIC project has taken a first step towards unlocking the power of a small set of integration processes, with cost-effective horizontal foundry access facilitated by an advanced user design interface. This will provide Europe with a lead in photonic integration and the basis for significant SME-led economic growth in a wide range of fields that are dependent upon photonic technology.
Cost-effective, automated and high-quality manufacturing
The major cost factors contributing to the total costs of a PIC are the investment costs of the cleanroom, the development costs of the semiconductor-based integration process, the costs of qualification and testing, the cost of packaging.
A large fab, such as the one owned by one of the partners, requires an investment of around 500 million for building the cleanroom and developing the processes. It could produce around 6000 3 wafers a year at full capacity, ultimately leading to chip costs of the order of EUR 3/mm2. For most, if not all fabs the total capacity is only partially used because the volume of today's applications is not large enough for the installed capacity. A number of fabs have opened their cleanrooms for developing components for so-called fabless customers. In this way the costs of the fab and part of the process development can be shared by several customers. This production model is called the custom foundry model, as opposed to the vertically integrated model where a foundry is exclusively used for products from the fab-owning company. Even if it can be based on available process know-how in the fab, investments in the order of 1 million or more are needed to adapt the process for the new product to the customer requirements. In the custom foundry model, sales volumes exceeding 10 000 pieces are required, therefore, for bringing the chip costs below EUR 100/chip. In combination with the required investment of more than 1M and the risk on future returns, this makes PICs unattractive for SMEs.
In the generic foundry model, which has been investigated and experimentally demonstrated in EUROPIC, not only the fab costs, but also the process development costs and the costs of qualification are shared by all customers, because a variety of ASPICs uses the same generic process. In this approach we are left with the costs of design and packaging. The costs of design will also be strongly reduced because in the applied methodology a variety of functions is synthesised from a small set of basic building blocks By properly characterising the performance of the basic building blocks, and implementing accurate models in a design tool, the designer can be relieved form a lot of work requiring detailed knowledge of the production process, and on the longer term single-cycle product design becomes feasible for a class of ASPICs that has been designed well within the design rules, just like in micro-electronics. And most of the laborious and expensive qualification procedure that is required to guarantee long term operation under harsh conditions is no longer necessary for each individual ASPIC, but can be restricted largely to the process itself and the basic building blocks. In this way the costs of design for ASPICs with moderate complexity can be reduced below 100 000, which will bring ASPIC costs in the 100 range already for volumes of a few thousand components. This will allow optical systems which presently cost several thousand Euros or more to be replaced with much cheaper integrated solutions. Innovative companies will accordingly be able to develop products for a wide range of applications at much lower cost, thereby stimulating growth.
Addressing new markets
Through its SME user group, which continues to be expanded with an active dissemination policy, EUROPIC expects to be able to address a variety of markets in which the costs of PICs are presently prohibitive for broad application. For example, in the project ASPICs have been fabricated with application in the following:
Sensors fibre-based sensors are a rapidly increasing market. In 2010, their volume exceeded USD 650 million, and estimates suggest that this could reach USD 3.31 billion in 2017. They play a key role in reducing environmental hazards by monitoring the integrity of large constructions like bridges, dykes, roofs of large buildings, windmill propeller blades, large reservoirs for storage of oil or chemicals, offshore platforms etc.
A new analysis from Frost and Sullivan, World Fiber Optic Sensors Markets, finds that the market earned revenues of USD 656.4 million in 2010 and estimates this to reach USD 3.31 billion in 2017. FO sensing also plays a critical role in other applications such as security, structural health monitoring, civil, industrial, energy, and defence.
In fibre-based sensors the readout unit usually contains InP-based sources, detectors and signal processing devices in expensive equipment, which often is far more expensive then the sensing fibre itself. ASPICs may substantially reduce the costs of this equipment and therefore open new markets with a value well over EUR 100 million. Two ASPICs have been designed by TU Eindhoven, and fabricated during the project; one at HHI, one at Oclaro. The first is a chip for measuring Brillouin scattering in a fibre attached to large engineering constructions for monitoring strain levels in the construction, the second a chip measuring the strain and temperature variations in fibre Bragg gratings.
Interconnect with the increasing processor speeds the need for photonic interconnect in computer backplanes is rapidly increasing and not only the interconnection, but also the switching should be performed in the optical domain. Fast photonic switches for Terabit server backplanes, HPC and multi-core architecture connections constitute a huge potential market for PICs addressed by a EUROPIC switch ASPIC. The market size for server backplanes is estimated to be approximately USD 150 million in 2008 and predicted to be USD 800 million by 2012. On board interconnects are anticipated to have a USD 4 billion market by 2012. Large data centre operators such as Google have also embraced optics as a route to managing the enormous data flows (and associated power demands) of modern computing. University of Cambridge has designs and tested a number of 4x4 port optical switch designs, built from semiconductor optical amplifier (SOA) based switching elements. This integrated switch is designed to operate as a transparent switch, being both lossless and transparent to the data-rate of the optical signals that it switches.
Telecommunications so far, telecommunications has been the main driver for PIC-development. Fibre based networks of increasing speed have been required to carry internet services, with increasingly more sophisticated use of bandwidth. To support this growth in data rates PICs of ever increasing complexity are required. The access market is especially interesting for a foundry approach because of the large market volumes which could run to many millions of chips in Europe alone. EUROPIC has addressed three ASPIC designs for access networks: one for application in a WDM fibre-to-the-home (FTTH) network, and two for radio-over-fibre (RoF) applications in wireless access. The WDM FTTH application addresses development of a chip that runs the communication with 20-40 subscribers in the central office. Further a fast tunable laser demonstrates the potential of the EUROPIC technology for demanding applications in the core or metro network.
Medical applications and signal processing the wavelength window around 1.5 μm, that can be addressed with InP-based ASPICs, is particularly relevant for diagnostic analysis of opaque tissue, because the penetration depths at these wavelengths are a factor of 3 higher than in the near IR window around 0.8μm, up to a few millimetres, due to lower scattering losses in the tissue. This is particularly relevant for analysis of suspect skin tissue or intra-arterial diagnostics, using techniques like optical coherence tomography (OCT) or Raman scatterometry. The market for OCT equipment presently exceeds 200 M. The market for Raman scatterometry is a factor of ten smaller, but if it is possible to integrate the Raman sensor on an InP-chip at a cost of a few hundred, it may be applied in a tool that will be in the diagnostic toolkit of a significant proportion of all doctors (more than a million for the EU alone). Another application is in non-linear microscopy where sub-picosecond pulses reveal properties of biological tissue that cannot be assessed in another way. Mode locked lasers are promising devices for producing the short pulses required for these applications, but they are also useful in high-speed data transmission and clock generation. The University of Cambridge has demonstrated for the first time an integrated, high quality, variable repetition rate short pulse source (mode locked laser) for bio-photonic applications with 109 MHz - 14 GHz repetition rates using the Oclaro platform.
These are just a few examples of the approximately 20 different ASPIC designs realised over the life of the project with a broad range of applications in mind. In addition to the existing consortium partners, EUROPIC has been careful to identify commercial exploitation routes for these developments and we are convinced that the ASPIC cost level targeted in EUROPIC will generate many more applications still. The market for ASPIC driven products could exceed the 1 Bn level within a decade and EUROPIC has taken an important step to provide Europe with a lead in this development.
Matching global regulatory requirements
By simplifying products, we eliminate many components that are conventionally needed, thereby reducing the use of materials and the corresponding environmental impact involved in their production. With regard to the semiconductor fabrication processes, by building all circuits on well proven, qualified processes we eliminate many yield hazards, thus maximising the number of chips that can be made per process run and again reducing materials use.
Transfer from research to industrial environment.
EUROPIC is a unique example for effective transfer of an approach that has been developed in a research environment (the ePIXnet network of excellence) to an industrial environment, by a consortium with a strong team of leading research and manufacturing partners. The roadmapping activity of EUROPIC and JePPIX will greatly enhance the effectiveness of transferring research results into industrial applications, by providing a clear picture to research partners where the technology development is expected to go.
Europe: world market leader
The economics of PIC production has been under intense pressure since the growth and collapse of the telecommunications bubble in 2001, leading to radical restructuring and consolidation of the photonics industry. New business models continue to be explored. At one extreme, systems companies such as Infinera have adopted a value chain based on intensive vertical integration, with their chips being the enabler for specific systems solutions. At the other extreme, we see the emergence of huge chip manufacturing organisations in the Far East, notably in China, serving diverse fields including solid state lighting and solar energy, as well as the kinds of photonic devices considered here. It will be very difficult for European and US companies to compete with such large fabs for manufacturing of simple commodity components. As is recognised by Horizon 2020, it is mandatory for Europe to move to technologies that require a significantly higher level of knowledge. A generic integration technology is such a technology, where knowledge translates to a high added value for advanced products. In the US, the emergence of the OPSIS organisation for Si photonics is a significant development. Through EUROPIC Europe has retained its lead in InP based technology and Europe is excellent position to become a world market leader for design and manufacturing of ASPICs.
Additional impacts
Moving from device R&D to circuit design and development
The creation of a generic technology base with a well defined user-interface will cause a shift from device-oriented R&D to circuit design and development. This will enable much more complex functionalities to be realised than is possible with today's device oriented approach. The impact of this development can hardly be over-estimated: it will open new fields of research on a much higher abstraction level than today's device engineering. In the long term, novel developments in the field of micro- and nano-lasers indicate that up to one million components per chip in digital applications may become feasible. This will enable applications that are far beyond our present imagination. The present project addresses a first crucial step in this direction.
Societal impact
Through a radical shift in thinking the achievements of the project stimulate high-technology, high-skill economic development across many sectors. In micro-electronics, which has adopted a foundry model, a lot of fabless IC companies have been very successful in Europe and high-value, high-skill jobs have been created. New applications, in health care, sensors, metrology and consumer devices, will themselves bring important social benefits. Many of the companies in these markets are SMEs and our project will stimulate the growth of this next generation of European industries maintaining high skill jobs for Europe, not only in the design and manufacturing of the photonic circuits themselves but particularly in the design and manufacturing of systems based upon them.
The market penetration of cost-effective ASPICs is expected to have an impact in many aspects of daily life. For example, in structural health monitoring with implications for safety and energy efficiency, in health, and in sensing, data transport and telecommunications where integrated solutions will be more energy efficient and can support more complex control systems such as in traffic flow.
European dimension
European regions that presently lack the relevant technological infrastructure, for example in the new member states, can gain access to the fabrication technology through the new EUROPIC business model which opens the way for them to take advantage of opportunities to develop and exploit advanced PICs. As part of the PARADIGM project a design hub centred on University of Warsaw has been created for precisely this purpose.
Countries such as France, Germany, the Netherlands, and the UK, have a strong history in photonics and semiconductor technology and in some partner countries such as the Netherlands, current funding policies at the national level have created a dynamic business community with many new high technology companies in this area.
Europe has shown that it can defend its markets well in high tech areas (see for example German strength in automotive engineering and in photonics) and we are confident that given suitable access to generic fab facilities, SMEs across Europe will take advance of the technology offered, keeping them competitive and indeed giving them a significant advantage on the world stage. So far Europe has the lead in this technology development and programmes such as EUROPIC help this to remain the case.
National and international activities
The project is intimately connected with the existing JePPIX platform. JePPIX, which has recently been appointed a part time coordinator at TU Eindhoven, provides for university-based training in design techniques and coordination of relevant research, as well as outreach to a wider user community in both academic and commercial spheres. EUROPIC proposes the GPICsLab concept to enable interested groups, particularly SMEs with related technical goals, to collaborate on ASPIC development in the pre-competitive phases of development. JePPIX will work with EUROPIC partners to set this up in the coming months, focusing around the needs of companies working in the fibre-based sensor area.
Dissemination activities and exploitation of results
EUROPIC has been very active in its dissemination of the foundry concept. It is represented in a Linked-in discussion group set up through JePPIX, and at the industry level through EPIC involvement.
Publications at conferences and in scientific papers:
In addition to material published on its public website (see http://EUROPIC.jeppix.eu online), EUROPIC has:
- in excess of 50 publications
- increasing numbers (approximately 15 in 2012 alone) of invited presentations on aspects of the generic fab show growing interest worldwide.
User based activities:
- three user group meetings have been held to date;
- six newsletters have been published;
- JePPIX roadmap 2012 published.
Training:
- course held in Eindhoven annually;
- broadly based, JePPIX-TU/e umbrella;
- two week introduction to photonic circuit technology, and chip design;
- attracts approximately 20 attendees each year.
Recognition of training needs alongside the developments in design environment and fab has been an important aspect of EUROPIC. Future training plans are continuing to mature alongside the PARADIGM project which features regular calls for applications groups external to the project to propose designs. Training courses have been continuously adapted to new platform requirements as they have developed. Many training sessions have been held by software partners on tools specific to EUROPIC, both to support existing consortium partners and other interested individuals, for example for training courses targeted at the EUROPIC run 2 designers hosted by PhoeniX in July 2011 and the project has launched a new one week focused, circuit based, design course to support new designers on the platform as part of its the training expansion programme.
Design manual
Controlled by NDA, the design manual is effectively a public document for those interested groups prepared to sign up. Setting up the means to distribute user level information such as the design manual, and information about the status of multi-project wafer runs has been an important aspect of the project.
PDAFlow API
The software, which is at the heart of the new design environment, will also be published though public release via and independent foundation, or Stichting, in the Netherlands.
Project website: http://EUROPIC.jeppix.eu
The EUROPIC project was set up to facilitate access by small companies to cost-effective indium phosphide based photonic integrated circuit (PIC) manufacture in Europe. Its objective was no less than to effect a fundamental change in the way applications based on PICs are designed and manufactured in Europe. This was to be achieved by developing a generic technology that is capable of realizing complex PICs from a small set of basic building blocks; a production model well known in micro-electronics where complex electronic circuits are built from standardized transistors and a small number of other elements.
The programme adopted a holistic approach, addressing the whole production chain from idea, via proof of concept, design and prototype to product and application. Research has been carried out into manufacturing methods and high-throughput processes, which will lead to an open-access industrial generic foundry production capability for Europe. The EUROPIC generic platform for manufacturing of PICs is based on InGaAsP materials technology (generally referred to as InP technology) which gives access to operating wavelengths typically used in telecommunications approximately 1.3 μm - 1.55 μm. EUROPIC has both set up the first generic foundry for InP-based PIC production in an industrial environment; and demonstrated its viability for small and medium-sized enterprises (SMEs). It has demonstrated the potential of the generic approach by fabricating a number of application specific PICs (ASPICs) concurrently on the same wafer- with high levels of complexity and performance, for a wide range of applications in telecommunications, sensors, data communications, medical systems, metrology and consumer photonics.
The completion of the EUROPIC programme heralds the start of a new chapter in the production of photonic integrated circuits. EUROPIC has not only successfully undertaken the first generic foundry run based on industrial (commercial) fabrication facilities at Oclaro (in the United Kingdom (UK)) and at FhG-HHI (in Germany), but also put in place most of the other elements of the production chain required to deliver it, and this for the first time.
Further, EUROPIC has built a strong user group, many of them SMEs, with committed users from different application fields, who will be actively involved in introducing cost-effective ASPICs in a variety of novel applications in the future, providing Europe with a competitive advantage over the United States (US) and the Far East.
Today, Europe's lead in this branch of photonics is clear, and InP-based PIC technology stands ready for full commercialisation.
Project context and objectives:
A summary description of project context and objectives.
Context
The EUROPIC project aimed to facilitate access by small companies to cost-effective InP-based PIC manufacture in Europe by setting up a generic fabrication platform based on industrial fabs.
At the beginnings of EUROPIC, it could be observed that despite large investments through national and international projects in Europe, America and the Far East, integrated photonics had far from fully redeemed its promises. The problem which EUROPIC set out to address was that the dominant working method in photonics was to develop optimised fabrication processes for each and every application, starting from the specifications of the product. As a result of this approach, there exist now almost as many fabrication technologies as applications. Due to this huge fragmentation in fabrication processes in relation to the associated market sizes, the cost price per product is far too high for a successful and sustainable introduction of products based on or including photonics components. In particular, the cost of entry is too high for most businesses. In order to create the breakthrough of photonics in a wide variety of application fields both the development cost and the unit cost need to be brought down by at least an order of magnitude.
The EUROPIC response was to create generic integrated technology for the research, development and manufacturing of ASPICs. Instead of optimising the fabrication technology for every specific application, the product design would be adapted to the capabilities of available, mature, high performance fabrication processes. This solution seems obvious in retrospect; we should introduce the same methodology to photonics that allowed micro-electronics to change the world since the eighties with CMOS technology.
CMOS, where a huge number of functions is reduced to a few elementary functions, which are performed by elementary building blocks like transistors, diodes, resistors and capacitors fabricated in a generic process, supports integration of these elementary building blocks in large numbers and in different circuit topologies. Therefore CMOS is capable of realising a wide variety of functions (chips) for a very broad range of applications. The fabrication processes can be made available via foundries to a large number of designers who use powerful design kits that allow fast and accurate design of the chips. In this way the large investments in development of the high-performance foundry processes can be shared by a large number of applications, resulting in a low cost price per product, thus enabling the current ubiquity of electronic integrated circuits.
Competing technologies for photonic integration have also advanced over the four years since the EUROPIC objectives were written; notably Si-photonics and the passive dielectric platform TriPleX. Silicon based photonics for example has demonstrated several key building block developments in the last few years using various technologies, but integration of these into the same CMOS compatible platform remains a significant challenge as does the provision of an on-chip optical source with reasonably high output power. The InP platform remains in a strong competitive position, and has high complementarity with the capabilities of Triplex.
Generic process
EUROPIC has addressed core aspects of this process chain, ranging from PIC design to consideration of approaches to generic packaging.
The methodology the consortium has applied to reach its project goals is:
- to decompose the functionality of complex photonic micro-systems into a small set of basic functions;
- to develop a building block for each of the basic functions and to develop production processes that are capable of integrating the basic building blocks in any arbitrary combination and number;
- to develop a dedicated design kit that contains an accurate model of the performance of the basic building blocks and that can simulate the response and the performance of complex circuits built from these building blocks as well as generate the mask layout;
- to develop dedicated measurement tools and vehicles for testing the quality and performance of the basic building blocks, in such a way that testing the performance of complex circuits is reduced to proper testing of the basic building blocks;
- to test the foundry concept with examples of high complexity ASPICs;
- to develop a small set of generic packages that can be used for a broad class of PICs, by introducing standardisation in the positions of optical and electrical connections, in chip dimensions and positioning of heat generating elements, which allows designers to work with them to work seamlessly in the design environment.
This methodology has been applied to two platforms, based on PIC fabrication, at the Fraunhofer HHI, Berlin and at Oclaro, UK respectively. It has delivered a generic integration technology at both.
Objectives
The project has achieved, or made significant progress, in all aspects of its initial objectives. In summary the project aimed to:
- to bring the application of photonic integrated micro-systems with a high added value in advanced products within reach for a broad class of SMEs by reducing the entrance costs dramatically by more than one order of magnitude;
- to enable the emergence of a new field of research in circuit-based photonic devices with ever increasing complexity and performance.
To demonstrate this, a number of target application PICs were produced, some constituting hero experiments in the technology, with a record combination of complexity and performance realised in a vastly reduced development time:
- to investigate novel technologies for extending the functionality supported by a basic manufacturing process;
- to shorten the R&D cycle time significantly by developing a software design kit with accurate models of the basic building blocks and their performance;
- to develop a generic test methodology that allows for a significant reduction of the effort required for testing and qualification, by testing the basic building blocks rather than specific PICs;
- to develop a generic packaging approach that allows for packaging a variety of different PICs with a small set of standardised packages;
- to develop a business model for a rapid but evolutionary introduction of the generic foundry approach in a number of application fields, mainly by and for SMEs.
Status
EUROPIC has not only successfully undertaken the first generic foundry run based on industrial (commercial) fabrication facilities at Oclaro (in the UK) and at FhG-HHI (in Germany), but also put in place many of the other elements of the production chain required to deliver this capability, and this for the first time. It has investigated new process methodologies and technologies capable of platform introduction in the future and new routes to generic packaging, going on to fabricate ASPICs of significant complexity and performance.
The ASPICs which result can take many forms, from a few basic building blocks such as waveguides, detectors, amplifiers and phase modulators to complex photonic chips with hundreds of building blocks can be designed and fabricated.
Project results:
Technical achievements
State of the art (start of project) EUROPIC target - Progress
- Developing specific manufacturing technology for each new PIC application
- Demonstration of the feasibility of a generic integration technology that allows for R&D&M of ten integrated micro-systems with a high added value for application in advanced photonic products.
- Chip development costs in multi-M- range even for relatively simple devices - Generic integration methodology to allow chip development cost reduction by at least one order of magnitude.
- Chip development timescales of several years - Put in place design tools and methodology to allow chip development times less than one year.
- PIC applications mainly in telecoms - Broaden applications to sensors, health, datacom, instrumentation, signal processing, and more.
- Few SMEs involved in new photonic device development - 100 SMEs involved in design and development of products containing novel photonic devices- 100 - strong user group. (Not all SMEs)
- Technology development slow despite large investment scceleration of technology development speed because of focused investment on a small set of broadly applicable technologies.
Objectives
EUROPIC has been successful or made significant progress against all of its objectives. The project has:
- successfully established the software-design-foundry work flow chain;
- software design kit built to support generic platform operation. The design kit features physical layer models and mask layout software. Integrated BB descriptions;
- platform supported by design manual for InP photonic circuits;
- circuit models ported through an API between different elements of the design toolkit;
- carried through the first generic platform run for InP PICs in Industry a key enabling step to achieve the programme objectives discussed above;
- approximately 20 different ASPIC designs realised on the platform with state-of the art complexity, plus 5 external user designs. Application level exploitation and demonstration of technology access for SMEs;
- demonstrated full BB transfer cycle onto the platform for AWG technology (both at FhG-HHI and Oclaro).
Another key objective for the project opening the path for future platform transfers. The project has also advanced several other technologies towards platform status; a theme which is expanded upon below.
- Worldwide awareness of photonic foundry operation raised significantly. But further technical work remains to be done to bring the platform to commercial realisation.
- Wafer validation (establishing the compliance of the finished wafer with accepted platform performance standards) - methodology not yet fully established.
- BB design data is still sketchy in places - more detailed and comprehensive building block characterisation is required.
- Generic test. Approaches to bar level test developed at Oclaro Technology have not yet worked through to full measurement data sets.
- Generic packaging chip daughterboard approach demonstrated. Generic design rules established. Performance (alignment accuracy) not yet established. Daughterboard motherboard integration (should be the simpler step) not yet demonstrated.
- Procedural / organisational aspects of the generic fab.
Generic fab concept
EUROPIC has created for the first time a foundry process for InP based photonic integrated circuits using industrial InP fab processes. A crucial aspect for photonic circuit designers has been to put in place a design environment to support easy access to the platform technology. In this technical report, we outline the technology which makes the InP based generic fab a reality.
Multi-project wafer runs
The methodology the consortium has applied is:
- to decompose the functionality of complex photonic micro-systems into a small set of basic functions;
- to develop a building block for each of the basic functions and to develop production processes that are capable of integrating the basic building blocks in any arbitrary combination and number;
- to develop a dedicated design kit that contains an accurate model of the performance of the basic building blocks and that can simulate the response and the performance of complex circuits built from these building blocks, as well as supporting mask layout;
- to develop dedicated measurement tools and vehicles for testing the quality and performance of the basic building blocks, in such a way that testing the performance of complex circuits is reduced to proper testing of the basic building blocks;
- to test the foundry concept with examples of high complexity ASPICs.
This methodology, which has been applied to two platforms, based on PIC fabrication at the Fraunhofer HHI, Berlin and at Oclaro, UK, has delivered a generic integration technology at both. At the conclusion of EUROPIC the HHI supported process is a receive side platform with passive components and a 40 GHz detector capability. The Oclaro platform meanwhile has a full transmit / receive capability but at 10 GHz.
Decomposition of the foundry process into elementary building blocks, and some more complex composite blocks, enables different ASPIC designs to be easily designed on the same platform and compiled into a single run a multi-project wafer run. The developed design environment, including all the software developments and definition of building blocks based on generic photonic integration technologies, has been extensively used and tested in such multi-project wafer runs (MPW run) and more than twenty different designs have been successfully created, originating from a wide variety of users, ranging from SMEs, research institutes, universities and large companies, and fabricated in separate runs by Oclaro and HHI.
EUROPIC design environment
Central to the operation of the design environment is the photonic design automation flow API - application programmers interface (PDAFlow API). The API created by EUROPIC contains the interface elements which enable physical layer design tools, such as Aspic from Filarete and PICWave from photon design, to work together with PhoeniX design tools and mask layout tools as if they were all part of an integrated package. The PDAFlow library also contains the calibrated building block descriptions for each platform.
The design environment
The design environment comprises the software environment, the design manual and the technology specific design kits. In the EUROPIC project, multi project wafer (MPW) runs for PICs fabricated in indium phosphide have been successfully implemented with the support of a design environment as created by partners Photon Design (UK), Filarete (Italy) and PhoeniX (the Netherlands). The software partners have developed a common platform to define photonic libraries and adopted their software solutions like PicWave, Aspic and MaskEngineer to be able to use these libraries or design kits for above named manufacturing sites. This has been done in close collaboration with the InP foundries at Oclaro and HHI.
The design kits contain all relevant information for designers to create a photonic integrated device or circuit within the capabilities of the fabrication processes. Users benefit from this by having immediate access to mature and proven building blocks, ensuring functional devices.
PDA flow API
One of the key aspects of this development has been to achieve interoperability of the software elements within the design environment. In the EUROPIC design kit, rather than having one very large and inflexible single piece of software, the unique properties and advantages of the different software packages are maintained. This allows for easier extension towards new software partners and also provides for a robust future proof approach. The required new approach is therefore that of being able to have the software elements 'talk together'; in software terminology an application programmers interface (API) for short.
Although the concept of an API is well established, both in general software engineering and applied in micro-electronics software tooling, this was not yet the case in micro-photonics. The EUROPIC project partners have developed a photonics domain specific API, called the PDAFlow-API. After the EUROPIC project end, this API has been be transferred to the ICT project PARADIGM (Seventh Framework Programme (FP7) ICT project No. 257210) for further development and in the near future it will be made available as a de-facto standard to interested parties through an independent foundation.
Design kits
Building blocks containing the geometrical information such as parameters, boundaries, design rules, intellectual property rights, simulation settings, mask information, and release version, have been created within the project. These building blocks give a designer the capability to design at a high abstraction level by using these 'standard' elements, provided by the manufacturing parties. In addition one can add additional constraints to this design, for instance by adding the boundary conditions imposed by the allowed chip sizes, package templates or packaging method. These building blocks are provided to the designers within the design environment, consisting of the software environment, the design manual and the technology specific design kit.
Design manual
An essential ingredient in the process flow is the design manual which enables the designer to access quickly the building blocks available in the platform. Design rules and standardised templates for packaging layouts are all supplied in the design manual and configured in the design tools for ease of use.
The design manual is one of the most critical achievements of the project. It encapsulates the foundry processes in a way which makes the technology immediately accessible to PIC designer; it has already been instrumental in enabling groups independent of EUROPIC to design onto the platforms.
API legal
During the EUROPIC project, a clear interest from groups outside the consortium was already visible and the results obtained within the project indicate the usefulness of the developed API for the future.
To optimally exploit the developed capability, use of the API will be extended as widely as possible within the photonics community, and since multiple definitions and/or multiple competing APIs would, if such existed, hinder the development of a successful photonics eco-system, the three key software parties in the consortium, Filarete, Photon Design and PhoeniX software have fixed upon the creation of a single legal entity to control the development and licensing of the PDAFlow API. A not for profit organisation will be created, structured as a legal entity in the Netherlands, a so called 'Stichting'. It is expected that the finalisation of the set-up of this 'Stichting' will take about four months from the end of the EUROPIC project. Contacts have already been established with potential partners both inside and outside the photonics field, which will allow a quick uptake into the academic community as well as with commercial software groups worldwide. At the time the legal entity is finalised, announcements will be made to the photonics community and one-on-one communication with relevant parties continued and new discussions initiated.
InP platform technology
EUROPIC has two InP fab partners, Oclaro and FhG-HHI, prepared to take up the challenging task of platform development. FhG-HHI can rely on a long-standing broad expertise in InP photonics technology. In particular, it reported the world's first fully integrated heterodyne receiver PIC as early as in 1994: at that time it was the most complex PIC ever made. FhG-HHI is now a world leader in high-speed receivers, amongst others. Oclaro has also long been a leader in this field, having published many innovative PIC designs and research results going back to the early 1990s, and many of Oclaro's advanced telecommunications products presently incorporate InP PIC technology.
Process research and exploitation in InP-based photonics requires access to world class fabrication facilities and these partners have opened up access to their production lines for this project.
Oclaro's clean rooms support a full-scale manufacturing facility at Caswell, UK, offering 57 000 ft2 (19 000 ft2 at class 10/100) of process space dedicated to a 3 InP process capability with a capacity exceeding 6000 wafers/year. The Caswell fab is one of the largest and best-equipped facilities worldwide dedicated to optoelectronic devices and circuits. Amongst the various process tools we may note six multi-wafer MOVPE reactors, e-beam lithography, plasma etch and deposition tools and extensive on-line control and diagnostic facilities.
FhG-HHI has successfully developed a wide range of different photonic devices (amongst them various types of laser diodes, ultra-fast photo-detectors, high-bit rate modulators, components for all-optical signal processing), in many cases in close cooperation with domestic and foreign SMEs. In offering PIC foundry developments and trial services FhG-HHI, through its photonic components department, brings into the project its entire R&D InP processing line comprising amongst many others such expensive equipment as a newly installed multi-wafer MOVPE reactor (8 x 2- 4), and a high resolution electron beam lithography apparatus.
In addition other composite elements are available such as AWGs. In this project there has been a strong focus on compatibility between building blocks in order to build optical circuits.
While both of the two platforms of Oclaro and FhG-HHI use 3 InP wafer technology, there are to-date still distinct technological differences; whereas Oclaro's platform builds on electrically conductive n+-substrate starting from their established and world-leading tunable laser and electro-optic modulator technology, FhG-HHI is using semi-insulating substrates (InP:Fe) starting from their proven high-speed waveguide-integrated photodetector technology. Accordingly the former platform mainly supports transmit and lower-frequency receive functions (10 GHz), whereas HHI's platform is focused on receiver-type PICs capable of 40 GHz bandwidth.
Application specific photonic integrated circuits realised
It was the aim of the project to validate the generic foundry approach by testing the whole production chain; the functionality and performance of the building blocks, the software design tools, the generic packaging and the viability of a set of challenging applications. With that aim two so-called multi-project wafer (MPW) runs have been scheduled in the project, one halfway and one at the end of the project. They have been carried out in the generic integration processes developed by EUROPIC partners Oclaro and Fraunhofer-HHI. MPWs are wafers on which a large number of ASPICs are combined in a single mask set and processed in a single wafer run. This concept, which is well known in micro-electronics, leads to a large reduction in R&D and product entry costs.
ASPICs from the first MPW-run became available in 2011. First results were very encouraging and have been published at a number of conferences (OFC 2012, ECIO 2012, CLEO 2012). A second MPW run, which contained both new ASPICs and improved redesigns of a number of the original ASPICs, has just completed fab at the end of the project. With these MPW-runs, which are the world's first InP-based generic foundry runs, EUROPIC has demonstrated the potential of the generic foundry model to bring photonic ICs within reach for many SMEs and large companies, by a dramatic reduction of the entry costs for developing complex photonic ICs.
Generic packaging of ASPICs in EUROPIC
Generic technology at the chip level requires a generic packaging approach which can accommodate most of the requirements set by chip designers for dc electrical, RF and optical I/O. In EUROPIC our approach has been based on the use of CIP's HyboardTM approach. Hyboard uses a patterned daughterboard made of silicon to carry the InP chip which is then positioned on a motherboard containing silica waveguides. The parts are then aligned passively. The fabrication of motherboards and daughterboards uses CIP's standard etching techniques for the daughterboards and flame hydrolysis deposition of silica on silicon for the motherboards. The designs have been developed in close collaboration with the InP PIC designers. They are used to package InP chips in the following way: the InP chip is flip chip bonded to the daughterboard, and this is then flipped again on to the motherboard. All the electrical connections are handled by the daughterboard, while all the optical interfaces are handled by the motherboard. The motherboard and daughterboards have been designed to be generic for all InP chip designs, provided a set of design constraints is followed. The exception to this is that the daughterboard metallisation is specific to a chip design, and is therefore laid out by the InP chip designer using a set of design rules to make it compatible with the daughterboard.
New semiconductor technology development
The generic platform technology must not be frozen in time, but should develop alongside the requirements of the users. EUROPIC has identified several technologies valuable in platform enhancement. The project has investigated the transfer of technology (building blocks) from an R&D base onto the platforms both at HHI and Oclaro in a number of specific cases. One can identify six maturity levels in new technology introduction onto the platform.
1. No established technology position in consortium
2. Demonstration at a technology house in the consortium
3. Technology assessed as ready to transfer as a building block
4. Demonstration of the building block in the platform process
5. Use in an ASPIC design by a circuit designer
6. ASPICs fabricated and tested using new BB
Building block- EUROPIC start- EUROPIC end
AWG technology BB - Level 2 - Level 6
Selective area growth (SAG) - Level 1 for Al(Q) - Level 3 continuation of technology platform introduction within PARADIGM project
Use of Al(Q) material - Level 2 - Level 4 - Use of Al(Q) for improved temperature performance will become standard in future platform releases.
Low PDL SOA based on Al(Q) - Level 1 - Level 3 - Source material demonstrated which can be fed into the platform at process start.
Polarisation rotators - Level 2 - Level 2/3 continuation of technology development within the PARADIGM project
Lasers on SI substrates (at HHI) - Level 1 - Level 4 (full platform introduction of the laser building block is an important part of the PARADIGM programme at HHI
Development of the platform at circuit level
Platform technology is multi-layered. New building blocks can be transferred into the platforms by the fab specialists whilst designers, independent of the underlying fab technology, can develop their own IP on the platform through the development of not just ASPIC designs, but also new building blocks, composites and photonic circuit libraries within the design environment. A good example of such a development within EUROPIC concerns the arrayed waveguide grating based devices.
Arrayed waveguide filters and multiplexers
A very important component in integrated optics is the arrayed waveguide grating (AWG). This component, effectively a prism, spatially (de)multiplexes light of different wavelengths in a photonic integrated circuit. The large number of constituent parts in AWGs and the required uniformity makes them very complex (circuit level) components.
The TU Eindhoven group has a long history with AWGs, dating back to their invention, and a lot of experience in the design and manufacture of this component. Within the EUROPIC project, a transfer of those capabilities to the Oclaro platform was achieved. In addition, the now commercially available BrightAWG module was successfully ported and tested in EUROPIC on the Oclaro and HHI platforms (it is also compatible with silicon on insulator (SoI) technology), and the resulting composite building block implemented in the design manual to allow easy access for designers. The result was excellent components that have already found their way into over 20 ASPIC designs within the EUROPIC project.
New business model
The separation of function with the generic fab leads to a new business model with the added advantage of clarification of legal responsibilities and IP ownership. Chip technology remains clearly owned by the fab and embedded calibration data can be hidden from the user in the software tools if necessary. Equally the fab can be application blind and as long as a circuit is platform compliant it can be fabricated without the fab having specific knowledge of its function. For immediate use, EUROPIC has developed an NDA; a one-to-many agreement, for use between the consortium and interested platform users.
New technology
Platform technology cannot stand still; it should evolve alongside the requirements of the user community. Major revisions and releases of new fab technology can occur on an occasional basis according to the platform roadmap (this point is covered in the subsection below). However, EUROPIC has also explored how new composite building blocks can be developed from existing ones (such as AWGs from passive waveguide building blocks) and how new technology building blocks can be introduced into the platform on a more evolutionary basis. Starting from a different technology provider partner there is a link formed with a fab partner to establish if a new BB can be platform compatible, and to fully characterize it. In addition, those responsible for the software design kits need to integrate the new capability into the design environment to make it available to the designers. A good example of such a development is the work on selective area growth which can extend the platforms to cover new wavelengths or extended wavelength ranges on a wafer.
Roadmaps
Working through JePPIX a roadmap for the generic fab development has been published for 2012.
The roadmap foresees first exploitation of the generic fab commercially through 2014 - 2015; however, the JePPIX platform and the fabs are already in close discussion about quasi-commercial activity to further trial the EUROPIC platform in 2013.
Summary
The EUROPIC consortium has taken an important first step in setting up a generic technology platform for ASPICs in InP using all industrial / commercial elements. Many successful designs have already been realised by project partners and a few by external groups trialing the platform. We stand at the threshold of commercialisation for this important technology.
The platform organisation JePPIX (the JePPIX coordinator is Luc Augustin, coordinator@jeppix.eu via e-mail) continues to promote the platform activities in Europe, whilst the ICT PARADIGM project seeks to extend the capability of the platforms through new technology introduction such as extensions to a full transmit and receive, and to a 40 G capability, also embracing a wider range of wavelength of operation.
Potential impact:
Potential impact of the EUROPIC project
We are confident that EUROPIC has already made a significant impact in many different spheres:
- academia through publications and invited talks;
- SMEs, large companies and academia through the user group and newsletters;
- web presence (websites of EUROPIC and JePPIX);
- social networking presence (LinkedIn);
- business potential through JePPIX and GPICsLab;
- personal contacts.
This view of a rapidly increasing level of interest in the generic fab is supported both by developments in the PARADIGM project where a very recent call for new users has attracted in excess of forty design proposals, and in the number of invited presentations at international conferences.
Introduction
PICs have shown an impressive increase in performance and complexity over the last two decades. But of the many components that have been investigated and reported by academic and industrial research labs very few have reached the commercial stage, so far. The main reason is that development of PICs is very expensive and large markets (typically well beyond 100 000 pieces) are required to pay back for the required investment. Such large markets can only be served by big companies, and even for them the commercial risks are high.
EUROPIC has aimed at investigation and experimental demonstration of a novel production paradigm that leads to a dramatic reduction of PIC research, development and manufacturing (R&D&M) costs by more than an order of magnitude. The expected cost reduction is such that it will bring the application of PICs in a variety of advanced products within reach for many SMEs. By doing this it lays the foundation for a dramatic expansion of the application spectrum and the market volume of PICs and novel or improved products that are enabled by or gain a competitive advantage by applying PICs for low-cost integration of complex functionality.
The EUROPIC project has taken a first step towards unlocking the power of a small set of integration processes, with cost-effective horizontal foundry access facilitated by an advanced user design interface. This will provide Europe with a lead in photonic integration and the basis for significant SME-led economic growth in a wide range of fields that are dependent upon photonic technology.
Cost-effective, automated and high-quality manufacturing
The major cost factors contributing to the total costs of a PIC are the investment costs of the cleanroom, the development costs of the semiconductor-based integration process, the costs of qualification and testing, the cost of packaging.
A large fab, such as the one owned by one of the partners, requires an investment of around 500 million for building the cleanroom and developing the processes. It could produce around 6000 3 wafers a year at full capacity, ultimately leading to chip costs of the order of EUR 3/mm2. For most, if not all fabs the total capacity is only partially used because the volume of today's applications is not large enough for the installed capacity. A number of fabs have opened their cleanrooms for developing components for so-called fabless customers. In this way the costs of the fab and part of the process development can be shared by several customers. This production model is called the custom foundry model, as opposed to the vertically integrated model where a foundry is exclusively used for products from the fab-owning company. Even if it can be based on available process know-how in the fab, investments in the order of 1 million or more are needed to adapt the process for the new product to the customer requirements. In the custom foundry model, sales volumes exceeding 10 000 pieces are required, therefore, for bringing the chip costs below EUR 100/chip. In combination with the required investment of more than 1M and the risk on future returns, this makes PICs unattractive for SMEs.
In the generic foundry model, which has been investigated and experimentally demonstrated in EUROPIC, not only the fab costs, but also the process development costs and the costs of qualification are shared by all customers, because a variety of ASPICs uses the same generic process. In this approach we are left with the costs of design and packaging. The costs of design will also be strongly reduced because in the applied methodology a variety of functions is synthesised from a small set of basic building blocks By properly characterising the performance of the basic building blocks, and implementing accurate models in a design tool, the designer can be relieved form a lot of work requiring detailed knowledge of the production process, and on the longer term single-cycle product design becomes feasible for a class of ASPICs that has been designed well within the design rules, just like in micro-electronics. And most of the laborious and expensive qualification procedure that is required to guarantee long term operation under harsh conditions is no longer necessary for each individual ASPIC, but can be restricted largely to the process itself and the basic building blocks. In this way the costs of design for ASPICs with moderate complexity can be reduced below 100 000, which will bring ASPIC costs in the 100 range already for volumes of a few thousand components. This will allow optical systems which presently cost several thousand Euros or more to be replaced with much cheaper integrated solutions. Innovative companies will accordingly be able to develop products for a wide range of applications at much lower cost, thereby stimulating growth.
Addressing new markets
Through its SME user group, which continues to be expanded with an active dissemination policy, EUROPIC expects to be able to address a variety of markets in which the costs of PICs are presently prohibitive for broad application. For example, in the project ASPICs have been fabricated with application in the following:
Sensors fibre-based sensors are a rapidly increasing market. In 2010, their volume exceeded USD 650 million, and estimates suggest that this could reach USD 3.31 billion in 2017. They play a key role in reducing environmental hazards by monitoring the integrity of large constructions like bridges, dykes, roofs of large buildings, windmill propeller blades, large reservoirs for storage of oil or chemicals, offshore platforms etc.
A new analysis from Frost and Sullivan, World Fiber Optic Sensors Markets, finds that the market earned revenues of USD 656.4 million in 2010 and estimates this to reach USD 3.31 billion in 2017. FO sensing also plays a critical role in other applications such as security, structural health monitoring, civil, industrial, energy, and defence.
In fibre-based sensors the readout unit usually contains InP-based sources, detectors and signal processing devices in expensive equipment, which often is far more expensive then the sensing fibre itself. ASPICs may substantially reduce the costs of this equipment and therefore open new markets with a value well over EUR 100 million. Two ASPICs have been designed by TU Eindhoven, and fabricated during the project; one at HHI, one at Oclaro. The first is a chip for measuring Brillouin scattering in a fibre attached to large engineering constructions for monitoring strain levels in the construction, the second a chip measuring the strain and temperature variations in fibre Bragg gratings.
Interconnect with the increasing processor speeds the need for photonic interconnect in computer backplanes is rapidly increasing and not only the interconnection, but also the switching should be performed in the optical domain. Fast photonic switches for Terabit server backplanes, HPC and multi-core architecture connections constitute a huge potential market for PICs addressed by a EUROPIC switch ASPIC. The market size for server backplanes is estimated to be approximately USD 150 million in 2008 and predicted to be USD 800 million by 2012. On board interconnects are anticipated to have a USD 4 billion market by 2012. Large data centre operators such as Google have also embraced optics as a route to managing the enormous data flows (and associated power demands) of modern computing. University of Cambridge has designs and tested a number of 4x4 port optical switch designs, built from semiconductor optical amplifier (SOA) based switching elements. This integrated switch is designed to operate as a transparent switch, being both lossless and transparent to the data-rate of the optical signals that it switches.
Telecommunications so far, telecommunications has been the main driver for PIC-development. Fibre based networks of increasing speed have been required to carry internet services, with increasingly more sophisticated use of bandwidth. To support this growth in data rates PICs of ever increasing complexity are required. The access market is especially interesting for a foundry approach because of the large market volumes which could run to many millions of chips in Europe alone. EUROPIC has addressed three ASPIC designs for access networks: one for application in a WDM fibre-to-the-home (FTTH) network, and two for radio-over-fibre (RoF) applications in wireless access. The WDM FTTH application addresses development of a chip that runs the communication with 20-40 subscribers in the central office. Further a fast tunable laser demonstrates the potential of the EUROPIC technology for demanding applications in the core or metro network.
Medical applications and signal processing the wavelength window around 1.5 μm, that can be addressed with InP-based ASPICs, is particularly relevant for diagnostic analysis of opaque tissue, because the penetration depths at these wavelengths are a factor of 3 higher than in the near IR window around 0.8μm, up to a few millimetres, due to lower scattering losses in the tissue. This is particularly relevant for analysis of suspect skin tissue or intra-arterial diagnostics, using techniques like optical coherence tomography (OCT) or Raman scatterometry. The market for OCT equipment presently exceeds 200 M. The market for Raman scatterometry is a factor of ten smaller, but if it is possible to integrate the Raman sensor on an InP-chip at a cost of a few hundred, it may be applied in a tool that will be in the diagnostic toolkit of a significant proportion of all doctors (more than a million for the EU alone). Another application is in non-linear microscopy where sub-picosecond pulses reveal properties of biological tissue that cannot be assessed in another way. Mode locked lasers are promising devices for producing the short pulses required for these applications, but they are also useful in high-speed data transmission and clock generation. The University of Cambridge has demonstrated for the first time an integrated, high quality, variable repetition rate short pulse source (mode locked laser) for bio-photonic applications with 109 MHz - 14 GHz repetition rates using the Oclaro platform.
These are just a few examples of the approximately 20 different ASPIC designs realised over the life of the project with a broad range of applications in mind. In addition to the existing consortium partners, EUROPIC has been careful to identify commercial exploitation routes for these developments and we are convinced that the ASPIC cost level targeted in EUROPIC will generate many more applications still. The market for ASPIC driven products could exceed the 1 Bn level within a decade and EUROPIC has taken an important step to provide Europe with a lead in this development.
Matching global regulatory requirements
By simplifying products, we eliminate many components that are conventionally needed, thereby reducing the use of materials and the corresponding environmental impact involved in their production. With regard to the semiconductor fabrication processes, by building all circuits on well proven, qualified processes we eliminate many yield hazards, thus maximising the number of chips that can be made per process run and again reducing materials use.
Transfer from research to industrial environment.
EUROPIC is a unique example for effective transfer of an approach that has been developed in a research environment (the ePIXnet network of excellence) to an industrial environment, by a consortium with a strong team of leading research and manufacturing partners. The roadmapping activity of EUROPIC and JePPIX will greatly enhance the effectiveness of transferring research results into industrial applications, by providing a clear picture to research partners where the technology development is expected to go.
Europe: world market leader
The economics of PIC production has been under intense pressure since the growth and collapse of the telecommunications bubble in 2001, leading to radical restructuring and consolidation of the photonics industry. New business models continue to be explored. At one extreme, systems companies such as Infinera have adopted a value chain based on intensive vertical integration, with their chips being the enabler for specific systems solutions. At the other extreme, we see the emergence of huge chip manufacturing organisations in the Far East, notably in China, serving diverse fields including solid state lighting and solar energy, as well as the kinds of photonic devices considered here. It will be very difficult for European and US companies to compete with such large fabs for manufacturing of simple commodity components. As is recognised by Horizon 2020, it is mandatory for Europe to move to technologies that require a significantly higher level of knowledge. A generic integration technology is such a technology, where knowledge translates to a high added value for advanced products. In the US, the emergence of the OPSIS organisation for Si photonics is a significant development. Through EUROPIC Europe has retained its lead in InP based technology and Europe is excellent position to become a world market leader for design and manufacturing of ASPICs.
Additional impacts
Moving from device R&D to circuit design and development
The creation of a generic technology base with a well defined user-interface will cause a shift from device-oriented R&D to circuit design and development. This will enable much more complex functionalities to be realised than is possible with today's device oriented approach. The impact of this development can hardly be over-estimated: it will open new fields of research on a much higher abstraction level than today's device engineering. In the long term, novel developments in the field of micro- and nano-lasers indicate that up to one million components per chip in digital applications may become feasible. This will enable applications that are far beyond our present imagination. The present project addresses a first crucial step in this direction.
Societal impact
Through a radical shift in thinking the achievements of the project stimulate high-technology, high-skill economic development across many sectors. In micro-electronics, which has adopted a foundry model, a lot of fabless IC companies have been very successful in Europe and high-value, high-skill jobs have been created. New applications, in health care, sensors, metrology and consumer devices, will themselves bring important social benefits. Many of the companies in these markets are SMEs and our project will stimulate the growth of this next generation of European industries maintaining high skill jobs for Europe, not only in the design and manufacturing of the photonic circuits themselves but particularly in the design and manufacturing of systems based upon them.
The market penetration of cost-effective ASPICs is expected to have an impact in many aspects of daily life. For example, in structural health monitoring with implications for safety and energy efficiency, in health, and in sensing, data transport and telecommunications where integrated solutions will be more energy efficient and can support more complex control systems such as in traffic flow.
European dimension
European regions that presently lack the relevant technological infrastructure, for example in the new member states, can gain access to the fabrication technology through the new EUROPIC business model which opens the way for them to take advantage of opportunities to develop and exploit advanced PICs. As part of the PARADIGM project a design hub centred on University of Warsaw has been created for precisely this purpose.
Countries such as France, Germany, the Netherlands, and the UK, have a strong history in photonics and semiconductor technology and in some partner countries such as the Netherlands, current funding policies at the national level have created a dynamic business community with many new high technology companies in this area.
Europe has shown that it can defend its markets well in high tech areas (see for example German strength in automotive engineering and in photonics) and we are confident that given suitable access to generic fab facilities, SMEs across Europe will take advance of the technology offered, keeping them competitive and indeed giving them a significant advantage on the world stage. So far Europe has the lead in this technology development and programmes such as EUROPIC help this to remain the case.
National and international activities
The project is intimately connected with the existing JePPIX platform. JePPIX, which has recently been appointed a part time coordinator at TU Eindhoven, provides for university-based training in design techniques and coordination of relevant research, as well as outreach to a wider user community in both academic and commercial spheres. EUROPIC proposes the GPICsLab concept to enable interested groups, particularly SMEs with related technical goals, to collaborate on ASPIC development in the pre-competitive phases of development. JePPIX will work with EUROPIC partners to set this up in the coming months, focusing around the needs of companies working in the fibre-based sensor area.
Dissemination activities and exploitation of results
EUROPIC has been very active in its dissemination of the foundry concept. It is represented in a Linked-in discussion group set up through JePPIX, and at the industry level through EPIC involvement.
Publications at conferences and in scientific papers:
In addition to material published on its public website (see http://EUROPIC.jeppix.eu online), EUROPIC has:
- in excess of 50 publications
- increasing numbers (approximately 15 in 2012 alone) of invited presentations on aspects of the generic fab show growing interest worldwide.
User based activities:
- three user group meetings have been held to date;
- six newsletters have been published;
- JePPIX roadmap 2012 published.
Training:
- course held in Eindhoven annually;
- broadly based, JePPIX-TU/e umbrella;
- two week introduction to photonic circuit technology, and chip design;
- attracts approximately 20 attendees each year.
Recognition of training needs alongside the developments in design environment and fab has been an important aspect of EUROPIC. Future training plans are continuing to mature alongside the PARADIGM project which features regular calls for applications groups external to the project to propose designs. Training courses have been continuously adapted to new platform requirements as they have developed. Many training sessions have been held by software partners on tools specific to EUROPIC, both to support existing consortium partners and other interested individuals, for example for training courses targeted at the EUROPIC run 2 designers hosted by PhoeniX in July 2011 and the project has launched a new one week focused, circuit based, design course to support new designers on the platform as part of its the training expansion programme.
Design manual
Controlled by NDA, the design manual is effectively a public document for those interested groups prepared to sign up. Setting up the means to distribute user level information such as the design manual, and information about the status of multi-project wafer runs has been an important aspect of the project.
PDAFlow API
The software, which is at the heart of the new design environment, will also be published though public release via and independent foundation, or Stichting, in the Netherlands.
Project website: http://EUROPIC.jeppix.eu
