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IntEgrated ModelliNg and Synthesis tOol flow for Embedded SYStems Design (ENOSYS)

Descrizione del progetto


Embedded Systems Design
To provide an integrated workbench that will increase productivity of embedded system development and shorten time-to-market for SoC systems
Today, SoC vendors realize that critical decisions must be made long before development teams engage in the hardware and software design for new SoC and programmable SoC-based products. It is becoming clear that hardware-software design and verification must form part of a single, unified effort, whereas the methodologies currently available were intended to aid either hardware-only or software-only development. That these tools are no longer adequate for modern SoC designs is confirmed by the recent emergence of new concepts that are disrupting the traditional design flow; these include system-level specification (specification capture), functional and architectural analysis, and high-level estimation, partitioning and software synthesis.
ENOSYS will provide an integrated workbench combining MARTE and FalconML. The OMG MARTE will be evaluated and extended to address end-user demands and requirements for integration. The approach and the tool flow will be evaluated and validated with representative scenarios from the telecoms domain. The results will be reported and presented at OMG in order to influence standardization and improve opportunities for adoption.

The main objectives of the ENOSYS project are to shorten time to market and reduce design costs in the development of new electronic products. This is of prime importance to European companies seeking to increase their share of the competitive consumer electronics market, where the flexibility to move quickly to add distinguishing features, such as faster operation, lower power consumption or miniaturization, is paramount. ENOSYS intends to achieve this by allowing designers to work at a high level of abstraction and removing the need to concentrate on the time-consuming details of the design.ENOSYS proposes a seamless tool flow for embedded systems modeling and synthesis and addresses the integration and enhancement of existing tools from European SME vendors (SOFTEAM and Axilica) to build a common extendable design environment. This will be delivered through: (a) the development of approaches for embedded system specification on different abstraction layers; (b) the development of efficient techniques for the exploration of the hardware/software design space and (c) the automatic synthesis of efficient descriptions for both hardware (synthesizable HDL) and embedded software (C/C++) components of the targeted system from models based on UML MARTE profile. To evaluate and to bring the proposed concepts to industrial application ENOSYS performs two complementary case studies (INTRACOM Telecom and THALES) covering wireless and/or multimedia application representing the future system complexity. Loughborough University and University of Peloponnese will deliver important new enhancements to improve performance and general applicability.Through active participation in the OMG standardization activities, results will be exploited both during the project and will persist long after completion. The partners will have the opportunity to transfer their actual design needs, stemming from real world cases studies in highly demanding application areas to emerging standards.

Invito a presentare proposte

FP7-ICT-2009-4
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Meccanismo di finanziamento

CP - Collaborative project (generic)

Coordinatore

SOFTEAM
Contributo UE
€ 679 530,00
Indirizzo
Avenue Victor Hugo 21
75016 PARIS
Francia

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Tipo di attività
Private for-profit entities (excluding Higher or Secondary Education Establishments)
Contatto amministrativo
Andrey Sadovykh (Dr.)
Collegamenti
Costo totale
Nessun dato

Partecipanti (5)